LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 225

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

5.8.1 First Dword
IT[2:0]
DSA
R
NF
LS
R
RA[6:0]
R
BC
Load and Store Instructions
Note:
Note:
This bit has no effect unless the Prefetch Enable bit in the
DMA Control (DCNTL)
(SFBR)
contents to another location.
It is not possible to Load the
Instruction Type
These bits should be 0b111, indicating the Load and
Store instruction.
DSA Relative
When this bit is cleared, the value in the
Pointer Save (DSPS)
used to perform the Load and Store to/from. When this
bit is set, the chip determines the memory address to
perform the Load and Store to/from by adding the 24-bit
signed offset value in the
(DSPS)
Reserved
No Flush (Store instruction only)
When this bit is set, the LSI53C825A performs a Store
without flushing the prefetch unit. When this bit is cleared,
the Store instruction automatically flushes the prefetch
unit. Use No Flush if the source and destination are not
within four instructions of the current Store instruction.
This bit has no effect on the Load instruction.
Load and Store
When this bit is set, the instruction is a Load. When
cleared, it is a Store.
Reserved
Register Address
A[6:0] selects the register to Load and Store to/from
within the LSI53C825A.
Reserved
Byte Count
This value is the number of bytes to Load and Store.
register, although it is possible to store the SFBR
to the
Data Structure Address
is the actual 32-bit memory address
register is set.
DMA SCRIPTS Pointer Save
SCSI First Byte Received
(DSA).
DMA SCRIPTS
[31:29]
[27:26]
[22:16]
[15:3]
[2:0]
[23]
5-41
28
25
24