LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 90

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Table 4.1
1. I/O Base is supported.
2. Memory Base is supported.
3. This register powers up enabled and can be disabled by pull-down resistors on the MAD5 pin.
4. If expansion memory is enabled through pull-down resistors on the MAD[7:0] bus.
Note: Addresses 0x40–7F are not defined for the LSI53C825A. Addresses 0x48–7F are not defined for
4-2
31
Not Supported
the LSI53C825AE. All unsupported registers are not writable and return all zeros when read.
Reserved registers also return zeros when read.
Max_Lat
Power Management Capabilities
Data
Subsystem ID (SSID)
PCI Configuration Register Map
Device ID
Base Address One (Memory)
Status
Base Address Zero (I/O)
Registers
Base Address Two (Memory) SCRIPTS RAM
Bridge Support
Header Type
Class Code
Extension
Reserved
Min_Gnt
Expansion ROM Base Address
Not Supported
Not Supported
Not Supported
Reserved
Reserved
16 15
1
SCSI Operating Registers
2
SCSI Operating Registers
Next Item Pointer
Latency Timer
Interrupt Pin
Power Management Control/Status
Subsystem Vendor ID (SSVID)
4
Command
Vendor ID
3
Capability Pointer
Cache Line Size
Interrupt Line
Capability ID
Revision ID
0
0x0C
0x1C
0x2C
0x3C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
0x40
0x44