LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 92

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-4
R
SE
R
EPER
R
WIE
R
EBM
EMS
Registers
Reserved
SERR/Enable
This bit enables the SERR/ driver. SERR/ is disabled
when this bit is clear. The default value of this bit is zero.
This bit and bit 6 must be set to report address parity
errors.
Reserved
Enable Parity Error Response
This bit allows the LSI53C825A to detect parity errors on
the PCI bus and report these errors to the system. Only
data parity checking is enabled. The LSI53C825A always
generates parity for the PCI bus.
Reserved
Write and Invalidate Mode
This bit, when set, causes Memory Write and Invalidate
cycles to be issued on the PCI bus after certain
conditions have been met. For more information on these
conditions, refer to
Invalidate Command.”
Mode, bit 10 in the
(operating register set) must also be set.
Reserved
Enable Bus Mastering
This bit controls the ability of the LSI53C825A to act as
a master on the PCI bus. A value of zero disables the
device from generating PCI bus master accesses. A
value of one allows the LSI53825A to behave as a bus
master. The LSI53C825A must be a bus master in order
to fetch SCRIPTS instructions and transfer data.
Enable Memory Space
This bit controls the ability of the LSI53C825A to respond
to Memory Space accesses. A value of zero disables the
device response. A value of one allows the LSI53C825A
to respond to Memory Space accesses at the address
specified by
Base Address One
Section 2.1.2.7, “Memory Write and
Chip Test Three (CTEST3)
To enable Write and Invalidate
(Memory).
register
[15:9]
8
7
6
5
4
3
2
1