LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 83

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Table 3.8
Name
BIG_LIT/ (Not
available on
LSI53C825AJ)
Additional Interface Signals (Cont.)
142, NA
Pin No.
PCI Bus Interface Signals
Type Description
I
Big_Little Endian Select. When this pin is driven LOW, the
LSI53C825A routes the first byte of an aligned SCSI to PCI
transfer to byte lane zero of the PCI bus and subsequent bytes
received are routed to ascending lanes. An aligned PCI to SCSI
transfer routes PCI byte lane zero onto the SCSI bus first, and
transfers ascending byte lanes in order. When this pin is driven
HIGH, the LSI53C825A routes the first byte of an aligned SCSI
to PCI transfer to byte lane three of the PCI bus and subsequent
bytes received are routed to descending lanes. An aligned PCI
to SCSI transfer routes PCI byte lane three onto the SCSI bus
first and transfer descending byte lanes in order. This mode of
operation also applies to the external memory interface. When
this pin is driven in little endian mode and the chip is performing
a read from external memory, the byte of data accessed at
location 0x00000 is routed to PCI byte lane zero and the data
accessed at location 0x00003 is routed to PCI byte lane three.
When the chip is performing a write to flash memory, PCI byte
lane zero is routed to location 0x00000 and ascending byte
lanes are routed to subsequent memory locations. When this
pin is driven in big endian mode and the chip is performing a
read from external memory, the byte of data accessed at
location 0x00000 is routed to PCI byte lane three and the data
accessed at location 0x00003 is routed to byte lane zero. When
the chip is performing a write to flash memory, PCI byte lane
three is routed to location 0x00000 and descending byte lanes
is routed to subsequent memory locations.
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