LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 116

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-28
WSR
Register: 0x03 (0x83)
SCSI Control Three (SCNTL3)
Read/Write
R
SCF[2:0]
Registers
R
7
0
6
0
count if the first byte received is one of the standard
group codes. If this bit is set, the device does not reload
the Block Move byte count, regardless of the group code.
Wide SCSI Receive
When read, this bit returns the value of the Wide SCSI
Receive (WSR) flag. Setting this bit clears the WSR flag.
This clearing function is self-clearing.
The WSR flag indicates that the SCSI core received data
from the SCSI bus, detected a possible partial transfer at
the end of a chained or nonchained block move
command, and temporarily stored the high-order byte in
the
passing the byte out the DMA channel. The hardware
uses the WSR status flag to determine what behavior
must occur at the start of the next data receive transfer.
When the flag is set, the stored data in SWIDE may be
“residue” data, valid data for a subsequent data transfer,
or overrun data. The byte is read as normal data by
starting a data receive transfer.
Performing a SCSI send operation clears this bit. Also,
performing any nonwide transfer clears this bit.
Reserved
Synchronous Clock Conversion Factor
These bits select a factor by which the frequency of
SCLK is divided before being presented to the
synchronous SCSI control logic. Write these to the same
value as the Clock Conversion Factor bits below unless
Fast SCSI operation is desired. See the
(SXFER)
SCF bits are used to calculate synchronous transfer
periods. See the table under the description of bits [7:5]
of the
combinations.
SCF[2:0]
SCSI Wide Residue (SWIDE)
SCSI Transfer (SXFER)
0
register description for examples of how the
4
0
EWS
3
0
register for the valid
2
0
register rather than
CCF[2:0]
SCSI Transfer
0
0
0
[6:4]
0
7