LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 27

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Table 2.1
1. This operation is selectable by bit 2 in the
2. This operation is selectable by bit 3 in the
3. This operation is selectable by bit 0 in the
2.1.2.1 I/O Read Command
2.1.2.2 I/O Write Command
C_BE[3:0] Command Type
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Special Interrupt Acknowledge
Special Cycle
I/O Read Cycle
I/O Write Cycle
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
PCI Bus Commands and Encoding Types
The I/O Read command reads data from an agent mapped in I/O
address space. All 32 address bits are decoded.
The I/O Write command writes data to an agent when mapped in I/O
address space. All 32 address bits are decoded.
PCI Addressing
DMA Mode (DMODE)
DMA Mode (DMODE)
Chip Test Three (CTEST3)
Supported as Master Supported as Slave
No
No
Yes
Yes
N/A
N/A
Yes
Yes
N/A
N/A
No
No
Yes
No
Yes
Yes
1
2
3
operating register.
operating register.
No
No
Yes
Yes
N/A
N/A
Yes
Yes
N/A
N/A
Yes
Yes
No (defaults to 0110)
No
No (defaults to 0110)
No (defaults to 0111)
operating register.
2-3