LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 93

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

EIS
Register: 0x06
Status
Read/Write
The
related events.
In the LSI53C825A, bits 0 through 4 are reserved and bits 5, 6, 7, and
11 are not implemented by the LSI53C825A.
Reads to this register behave normally. Writes are slightly different in that
bits can be cleared, but not set. A bit is reset whenever the register is
written, and the data in the corresponding bit location is a one. For
instance, to clear bit 15 and not affect any other bits, write the value
0x8000 to the register.
DPE
SSE
RMA
RTA
Configuration Registers
DPE SSE RMA RTA
15
0
Status
14
0
13
0
register is used to record status information for PCI bus
12
0
Enable I/O Space
This bit controls the LSI53C825A response to I/O space
accesses. A value of zero disables the response. A value
of one allows the LSI53C825A to respond to I/O space
accesses at the address specified in
(Memory).
Detected Parity Error (from Slave)
This bit is set by the LSI53C825A whenever it detects a
data parity error, even if parity error handling is disabled.
Signaled System Error
This bit is set whenever a device asserts the SERR/
signal.
Received Master Abort (from Master)
A master device should set this bit whenever its
transaction (except for Special Cycle) is terminated with
master abort.
Received Target Abort (from Master)
A master device should set this bit whenever its
transaction is terminated with a target abort.
11
R
0
10
DT[1:0]
0
9
0
DPR
8
0
7
0
R
0
5
0
NC
4
1
Base Address One
3
0
0
R
0
4-5
0
0
15
14
13
12
0