LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 296

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

SCSI
IX-6
ATN condition - target mode (M/A)
bus control lines (SBCL)
bus data lines (SBDL)
C_D/ signal (C_D)
chip ID (SCID)
clock (SCLK)
control enable (SCE)
control one (SCNTL1)
control three (SCNTL3)
control two (SCNTL2)
control zero (SCNTL0)
core
data high impedance (ZSD)
destination ID (SDID)
differential mode
disconnect unexpected (SDU)
encoded destination ID
FIFO test read (STR)
FIFO test write (STW)
first byte received (SFBR)
gross error (SGE)
I_O/ signal (I/O)
input data latch (SIDL)
instructions
interrupt enable one (SIEN1)
interrupt enable zero (SIEN0)
interrupt pending (SIP)
interrupt status one (SIST1)
interrupt status zero (SIST0)
isolation mode (SISO)
longitudinal parity (SLPAR)
loopback mode (SLB)
low level mode (LOW)
MSG/ signal (MSG)
output control latch (SOCL)
output data latch (SODL)
parity error (PAR)
phase
phase mismatch - initiator mode
reset condition (RST)
RST/ received (RST)
RST/ signal (RST)
SDP0/ parity signal (SDP0)
SDP1/ parity signal (SDP1)
selected as ID (SSAID[3:0])
selector ID (SSID)
signals
status one (SSTAT1)
status two (SSTAT2)
status zero (SSTAT0)
synchronous offset maximum (SOM)
synchronous offset zero (SOZ)
synchronous transfer period (TP[2:0])
termination
test one (STEST1)
test three (STEST3)
test two (STEST2)
test zero (STEST0)
timer one (STIME1)
timer zero (STIME0)
TolerANT technology
transfer (SXFER)
true end of process
I/O
read/write
2-10
5-12
5-14
3-10
,
2-29
5-33
4-87
5-24
4-30
4-45
2-28
4-31
4-72
4-71
4-39
4-45
4-44
4-88
4-87
4-86
4-54
4-45
4-83
4-90
4-81
4-46
4-88
4-75
4-44
1-3
4-35
4-72
4-90
4-26
4-88
4-43
4-23
4-87
4-93
4-91
,
4-89
4-20
4-92
4-50
5-22
4-28
Index
4-74
4-39
4-93
4-37
4-77
4-44
4-47
4-38
4-57
4-76
4-86
4-73
4-72
4-70
4-26
4-86
4-71
4-71
4-87
4-31
SCSI bus interface
SCSI core
SCSI instructions
SCSI SCRIPTS operation
SCSI-1 transfers (differential 4.17 Mbytes)
SCSI-1 transfers (single-ended 5.0 Mbytes)
SCSI-2 fast transfers 10.0 Mbytes (8-bit transfers) or 20.0
SCSI-2 fast transfers 10.0 Mbytes (8-bit transfers) or 20.0
second dword
select
selected (SEL)
selection or reselection time-out (STO)
selection response logic test (SLT)
semaphore (SEM)
set instruction
set/clear
shadow register test mode (SRTM)
SIDL
signal process (SIGP)
signals
simple arbitration
single
single-ended operation
SLPAR high byte enable (SLPHBEN)
SLPAR mode (SLPMD)
SODL
SODR
software reset (SRST)
source
stacked interrupts
start
Storage Device Management System (SDMS)
stress ratings
subsystem ID
subsystem vendor ID
valid (VAL)
wide residue (SWIDE)
block move
sample instruction
Mbytes (16-bit transfers) 40 MHz clock
Mbytes (16-bit transfers) 50 MHz clock
instruction
with ATN/
with SATN/ on a start sequence (WATN)
carry
SACK/
least significant byte full (ILF)
most significant byte full (ILF1)
address and data signals
arbitration signals
error reporting signals
interface control signals
SCSI signals
step interrupt (SSI)
step mode (SSM)
least significant byte full (OLF)
most significant byte full (OLF1)
least significant byte full (ORF)
most significant byte full (ORF1)
I/O-memory enable (SIOM)
address
DMA operation (STD)
SCSI transfer (SST)
sequence (START)
(SID[15:0])
(SVID[15:0])
5-22
2-10
5-23
5-13
6-2
5-22
5-13
5-18
5-16
4-11
4-71
4-39
5-6
4-10
,
3-10
4-20
2-39
4-49
5-23
,
,
2-27
,
5-19
5-23
4-74
3-9
4-69
5-3
4-49
4-49
4-41
2-27
4-21
4-27
4-25
to
,
4-69
5-2
3-9
4-78
,
5-26
,
3-8
2-33
4-53
3-7
4-67
4-65
,
4-43
5-36
4-43
4-46
4-43
4-86
4-58
4-46
4-46
4-27
,
4-73
5-38
6-49
6-50
6-50
,
6-49
,
4-22
4-76
2-12
5-42