MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 120

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Monitor ROM (MON)
8.3.2 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
8.3.3 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal,
it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
8.3.4 Baud Rate
The communication baud rate is controlled by the crystal frequency and the state of the PTB0 pin (when
IRQ1 is set to V
PTB0 pin is at logic 0 upon entry into monitor mode, the divide by ratio is 512.
If monitor mode was entered with V
This condition for monitor mode entry requires that the reset vector is blank.
Table 8-3
standard baud rates can be accomplished using proportionally higher or lower frequency generators. If
using a crystal as the clock source, be aware of the upper frequency limit that the internal clock module
can handle.
120
lists external frequencies required to achieve a standard baud rate of 9600 BPS. Other
START
TST
BIT
4.9152 MHz
9.8304 MHz
9.8304 MHz
Frequency
32.768 kHz
External
) upon entry into monitor mode. When PTB0 is high, the divide by ratio is 1024. If the
0
BIT 0
1
2
MISSING STOP BIT
BIT 1
3
Table 8-3. Monitor Baud Rate Selection
MC68HC908AP Family Data Sheet, Rev. 4
4
DD
Figure 8-3. Monitor Data Format
IRQ1
BIT 2
V
V
V
V
Figure 8-4. Break Transaction
TST
TST
DD
SS
5
on IRQ1, then the divide by ratio is set at 1024, regardless of PTB0.
6
BIT 3
7
PTB0
X
X
0
1
BIT 4
BIT 5
2-STOP BIT DELAY BEFORE ZERO ECHO
2.4576 MHz
2.4576 MHz
2.4576 MHz
2.4576 MHz
Frequency
Internal
BIT 6
0
1
BIT 7
2
3
STOP
BIT
4
Baud Rate
5
START
NEXT
(BPS)
9600
9600
9600
9600
BIT
6
Freescale Semiconductor
7