MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 97

no-image

MC908AP32CFBE

Manufacturer Part Number
MC908AP32CFBE
Description
Manufacturer
Freescale
Datasheet

Specifications of MC908AP32CFBE

Cpu Family
HC08
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
32
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
32KB
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908AP32CFBE
Manufacturer:
Freescale
Quantity:
6
Part Number:
MC908AP32CFBE
Manufacturer:
FREESCALE
Quantity:
5 000
Part Number:
MC908AP32CFBE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC908AP32CFBE
Manufacturer:
FREESCALE
Quantity:
5 000
Part Number:
MC908AP32CFBE
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC908AP32CFBE
Quantity:
96
Part Number:
MC908AP32CFBER
Manufacturer:
FREESCALE
Quantity:
5 000
Part Number:
MC908AP32CFBER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 7
System Integration Module (SIM)
7.1 Introduction
This section describes the system integration module (SIM). Together with the CPU, the SIM controls all
MCU activities. A block diagram of the SIM is shown in
input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
Table 7-1
Freescale Semiconductor
CGMVCLK, CGMPCLK
Bus clock generation and control for CPU and peripherals:
Master reset control, including power-on reset (POR) and COP timeout
Interrupt control:
CPU enable/disable timing
Modular architecture expandable to 128 interrupt sources
Signal Name
CGMXCLK
CGMOUT
PORRST
shows the internal signal names used in this section.
Stop/wait/reset/break entry and recovery
Internal clock control
Acknowledge timing
Arbitration control timing
Vector address generation
ICLK
IRST
R/W
IDB
IAB
Internal oscillator clock
Selected oscillator clock from oscillator module
PLL output and the divided PLL output
CGMPCLK-based or oscillator-based clock output from CGM module
(Bus clock = CGMOUT ÷ 2)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
Table 7-1. Signal Name Conventions
MC68HC908AP Family Data Sheet, Rev. 4
Figure
Description
7-1.
Figure 7-2
is a summary of the SIM
97

Related parts for MC908AP32CFBE