MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 204

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Infrared Serial Communications Interface Module (IRSCI)
OR — Receiver Overrun Bit
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it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit.
Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle
condition can set the IDLE bit. Reset clears the IDLE bit.
This clearable, read-only bit is set when software fails to read the IRSCDR before the receive shift
register receives the next character. The OR bit generates an SCI error CPU interrupt request if the
ORIE bit in IRSCC3 is also set. The data in the shift register is lost, but the data already in the IRSCDR
is not affected. Clear the OR bit by reading IRSCS1 with OR set and then reading the IRSCDR. Reset
clears the OR bit.
Software latency may allow an overrun to occur between reads of IRSCS1 and IRSCDR in the
flag-clearing sequence.
overrun caused by a delayed flag-clearing sequence. The delayed read of IRSCDR does not clear the
OR bit because OR was not set when IRSCS1 was read. Byte 2 caused the overrun and is lost. The
next flag-clearing sequence reads byte 3 in the IRSCDR instead of byte 2.
In applications that are subject to software latency or in which it is important to know which byte is lost
due to an overrun, the flag-clearing routine can check the OR bit in a second read of IRSCS1 after
reading the data register.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
BYTE 1
BYTE 1
READ IRSCDR
READ IRSCS1
Figure 12-16
SCRF = 1
BYTE 1
OR = 0
Figure 12-16. Flag Clearing Sequence
MC68HC908AP Family Data Sheet, Rev. 4
READ IRSCDR
READ IRSCS1
DELAYED FLAG CLEARING SEQUENCE
NORMAL FLAG CLEARING SEQUENCE
BYTE 2
BYTE 2
SCRF = 1
BYTE 1
shows the normal flag-clearing sequence and an example of an
OR = 0
READ IRSCDR
READ IRSCS1
SCRF = 1
BYTE 2
OR = 0
BYTE 3
BYTE 3
READ IRSCDR
READ IRSCDR
READ IRSCS1
READ IRSCS1
SCRF = 1
SCRF = 1
BYTE 3
BYTE 3
OR = 1
OR = 0
BYTE 4
BYTE 4
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