MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 289

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Chapter 20
Low-Voltage Inhibit (LVI)
20.1 Introduction
This section describes the low-voltage inhibit (LVI) module. The LVI module monitors the voltage on the
V
below V
20.2 Features
Features of the LVI module include:
20.3 Functional Description
Figure 20-2
contains independent bandgap reference circuit and comparator for monitoring the V
V
low-voltage protection to external peripheral devices.
LVISTOP, LVIPWRD, LVIRSTD, and LVIREGD are in the CONFIG1 register. See
Configuration & Mask Option Registers (CONFIG & MOR)
Freescale Semiconductor
$FE0F
Addr.
DD
REG
•
•
•
•
pin and V
voltage. An LVI reset performs a MCU internal reset and drives the RST pin low to provide
Independent voltage monitoring circuits for V
Independent disable for V
Programmable LVI reset
Programmable stop mode operation
TRIPF2
Register Name
shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module
LVI Status Register
REG
.
The V
guaranteed to meet operating specification as long as V
MCU operating voltage.
The LVI feature is intended to provide the safe shutdown of the
microcontroller and thus protection of related circuitry prior to any
application V
intended that users operate the microcontroller at lower than the specified
operating voltage, V
pin, and can force a reset when V
REG
(LVISR)
pin is the output of the internal voltage regulator and is
DD
Reset:
Read:
Write:
voltage collapsing completely to an unsafe level. It is not
Figure 20-1. LVI I/O Register Summary
DD
MC68HC908AP Family Data Sheet, Rev. 4
LVIOUT
DD
Bit 7
and V
0
.
REG
= Unimplemented
6
0
0
LVI circuits
NOTE
DD
DD
5
0
0
and V
voltage falls below V
for details of the LVI configuration bits. Once
REG
4
0
0
DD
3
0
0
is within the
TRIPF1
2
0
0
, or V
Chapter 3
DD
REG
voltage and the
1
0
0
voltage falls
Bit 0
0
0
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