MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 89
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MC908AP32CFBE
Manufacturer Part Number
MC908AP32CFBE
Description
Manufacturer
Freescale
Datasheet
1.MC908AP32CFBE.pdf
(324 pages)
Specifications of MC908AP32CFBE
Cpu Family
HC08
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
32
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
32KB
Lead Free Status / RoHS Status
Compliant
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6.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base
clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits.
PLLIE — PLL Interrupt Enable Bit
PLLF — PLL Interrupt Flag Bit
PLLON — PLL On Bit
BCS — Base Clock Select Bit
Freescale Semiconductor
This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting
the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE
cannot be written and reads as logic 0. Reset clears the PLLIE bit.
This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the
PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control
register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF
bit.
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be
cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See
Selector
This read/write bit selects either the oscillator output, CGMXCLK, or the divided VCO clock,
CGMPCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the
frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS,
it may take up to three CGMXCLK and three CGMPCLK cycles to complete the transition from one
source clock to the other. During the transition, CGMOUT is held in stasis. (See
Selector
1 = PLL interrupts enabled
0 = PLL interrupts disabled
1 = Change in lock condition
0 = No change in lock condition
1 = PLL on
0 = PLL off
1 = CGMPCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up.
Circuit.) Reset clears the BCS bit.
Address:
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
Reset:
Read:
Write:
$0036
PLLIE
Bit 7
0
Figure 6-4. PLL Control Register (PCTL)
=
PLLF
Unimplemented
6
0
MC68HC908AP Family Data Sheet, Rev. 4
PLLON
5
1
NOTE
BCS
4
0
PRE1
3
0
PRE0
2
0
VPR1
1
0
6.3.8 Base Clock
6.3.8 Base Clock
VPR0
Bit 0
0
CGM Registers
89
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