MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 31

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
$000A
$000B
$000C
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
Addr.
Port C Data Register (PTC)
Port D Data Register (PTD)
Data Direction Register C
Data Direction Register D
Data Direction Register A
Data Direction Register B
Register Name
Port A Data Register
Port B Data Register
Port-A LED Control
Unimplemented
Unimplemented
Unimplemented
Unimplemented
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 9)
Register
(DDRC)
(DDRD)
(DDRA)
(DDRB)
(LEDA)
(PTA)
(PTB)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
X = Indeterminate
MC68HC908AP Family Data Sheet, Rev. 4
DDRA7
DDRB7
DDRC7
DDRD7
LEDA7
PTC7
PTD7
PTA7
PTB7
Bit 7
0
0
0
0
0
DDRA6
DDRB6
DDRC6
DDRD6
LEDA6
PTC6
PTD6
PTA6
PTB6
6
0
0
0
0
0
DDRA5
DDRB5
DDRC5
DDRD5
LEDA5
PTC5
PTD5
PTA5
PTB5
5
0
0
0
0
0
= Unimplemented
DDRA4
DDRB4
DDRC4
DDRD4
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
LEDA4
PTA4
PTB4
PTC4
PTD4
4
0
0
0
0
0
DDRC3
DDRD3
DDRA3
DDRB3
LEDA3
PTA3
PTB3
PTC3
PTD3
3
0
0
0
0
0
DDRC2
DDRD2
DDRA2
DDRB2
LEDA2
PTA2
PTB2
PTC2
PTD2
R
2
0
0
0
0
0
= Reserved
DDRC1
DDRD1
DDRA1
DDRB1
LEDA1
PTA1
PTB1
PTC1
PTD1
1
0
0
0
0
0
Monitor ROM
DDRA0
DDRB0
DDRC0
DDRD0
LEDA0
PTA0
PTB0
PTC0
PTD0
Bit 0
0
0
0
0
0
31