MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 29

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Chapter 2
Memory
2.1 Introduction
The CPU08 can address 64k-bytes of memory space. The memory map, shown in
2.2 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page area of $0000–$005F. Additional I/O
registers have these addresses:
2.3 Monitor ROM
The 959 bytes at addresses $FC00–$FDFF and $FE10–$FFCE are reserved ROM addresses that
contain the instructions for the monitor functions. (See
Freescale Semiconductor
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62,368 bytes of user FLASH — MC68HC908AP64
32,768 bytes of user FLASH — MC68HC908AP32
16,384 bytes of user FLASH — MC68HC908AP16
8,192 bytes of user FLASH — MC68HC908AP8
2,048 bytes of RAM — MC68HC908AP64 and MC68HC908AP32
1,024 bytes of RAM — MC68HC908AP16 and MC68HC908AP8
48 bytes of user-defined vectors
959 bytes of monitor ROM
$FE00; SIM break status register, SBSR
$FE01; SIM reset status register, SRSR
$FE02; Reserved
$FE03; SIM break flag control register, SBFCR
$FE04; interrupt status register 1, INT1
$FE05; interrupt status register 2, INT2
$FE06; interrupt status register 3, INT3
$FE07; Reserved
$FE08; FLASH control register, FLCR
$FE09; FLASH block protect register, FLBPR
$FE0A; Reserved
$FE0B; Reserved
$FE0C; Break address register high, BRKH
$FE0D; Break address register low, BRKL
$FE0E; Break status and control register, BRKSCR
$FE0F; LVI Status register, LVISR
$FFCF; Mask option register, MOR (FLASH register)
$FFFF; COP control register, COPCTL
MC68HC908AP Family Data Sheet, Rev. 4
Chapter 8 Monitor ROM
(MON).)
Figure
2-1, includes:
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