MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 257

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

ADICLK — ADC Input Clock Select Bit
MODE1 and MODE0 — Modes of Result Justification
15.7.3 ADC Data Register 0 (ADRH0 and ADRL0)
The ADC data register 0 consist of a pair of 8-bit registers: high byte (ADRH0), and low byte (ADRL0).
This pair form a 16-bit register to store the 10-bit ADC result for the selected ADC result justification mode.
In 8-bit truncated mode, the ADRL0 holds the eight most significant bits (MSBs) of the 10-bit result. The
ADRL0 is updated each time an ADC conversion completes. In 8-bit truncated mode, ADRL0 contains no
interlocking with ADRH0. (See
Freescale Semiconductor
ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC
clock. Reset selects CGMXCLK as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1MHz, CGMXCLK can be used as the
clock source for the ADC. If CGMXCLK is less than 1MHz, use the PLL-generated bus clock as the
clock source. As long as the internal ADC clock is at f
MODE1 and MODE0 selects between four modes of operation. The manner in which the ADC
conversion results will be placed in the ADC data registers is controlled by these modes of operation.
Reset returns right-justified mode.
1 = Internal bus clock
0 = External clock, CGMXCLK
f
ADIC
X = don’t care
ADIV2
=
0
0
0
0
1
MODE1
0
0
1
1
Figure 15-5 . ADRH0 and ADRL0 in 8-Bit Truncated
CGMXCLK or bus frequency
Table 15-2. ADC Clock Divide Ratio
MC68HC908AP Family Data Sheet, Rev. 4
ADIV1
X
Table 15-3. ADC Mode Select
0
0
1
1
MODE0
ADIV[2:0]
0
1
0
1
ADIV0
X
0
1
0
1
8-bit truncated mode
Right justified mode
Left justified mode
Left justified sign data mode
Justification Mode
ADIC
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
, correct operation can be guaranteed.
ADC Clock Rate
Mode.)
I/O Registers
255