MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 49

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Chapter 3
Configuration & Mask Option Registers (CONFIG & MOR)
3.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2; and the mask option
register, MOR.
The configuration registers enable or disable these options:
The mask option register selects one of the following oscillator options:
Freescale Semiconductor
$001D
$001F
$FFCF
† One-time writable register after each reset.
#
Addr.
MOR is a non-volatile FLASH register; write by programming.
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•
•
•
•
•
•
•
•
•
•
•
•
Computer operating properly module (COP)
COP timeout period (2
Low-voltage inhibit (LVI) on V
LVI on V
LVI module reset
LVI module in stop mode
STOP instruction
Stop mode recovery time (32 ICLK or 4096 ICLK cycles)
Oscillator (internal, RC, and crystal) during stop mode
Serial communications interface clock source (CGMXCLK or f
Internal oscillator
RC oscillator
Crystal oscillator
Configuration Register 2
Configuration Register 1
Register Name
Mask-Option-Register
REG
(CONFIG2)
(CONFIG1)
(MOR)
Figure 3-1. CONFIG and MOR Registers Summary
†
†
#
Erased:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
18
– 2
OSCSEL1 OSCSEL0
MC68HC908AP Family Data Sheet, Rev. 4
ICLKDIS
COPRS
STOP_
4
Bit 7
DD
or 2
0
0
1
13
= Unimplemented
LVISTOP
RCLKEN
– 2
STOP_
6
0
0
1
4
ICLK cycles)
LVIRSTD
XCLKEN
STOP_
R
5
0
0
1
OSCCLK1 OSCCLK0
LVIPWRD
R
4
0
0
1
BUS
LVIREGD
R
R
)
3
0
0
1
= Reserved
SSREC
R
2
0
0
0
1
STOP
R
1
0
0
0
1
SCIBDSRC
COPD
Bit 0
R
0
0
1
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