MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 267
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MC908AP32CFBE
Manufacturer Part Number
MC908AP32CFBE
Description
Manufacturer
Freescale
Datasheet
1.MC908AP32CFBE.pdf
(324 pages)
Specifications of MC908AP32CFBE
Cpu Family
HC08
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
32
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
32KB
Lead Free Status / RoHS Status
Compliant
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When DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When DDRBx is a logic 0,
reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Table 16-3
16.4 Port C
Port C is an 8-bit special-function port that shares one of its pins with the IRQ2, four of its pins with the
SPI module, and two of its pins with the IRSCI module.
16.4.1 Port C Data Register (PTC)
The port C data register contains a data latch for each of the eight port C pins.
Freescale Semiconductor
Alternative Function:
summarizes the operation of the port B pins.
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect input.
DDRB
Bit
0
1
Address:
Reset:
Read:
Write:
READ DDRB ($0005)
WRITE DDRB ($0005)
WRITE PTB ($0001)
READ PTB ($0001)
PTB Bit
X
X
(1)
SCRxD
$0002
PTC7
Bit 7
Figure 16-9. Port C Data Register (PTC)
I/O Pin Mode
Input, Hi-Z
MC68HC908AP Family Data Sheet, Rev. 4
Table 16-3. Port B Pin Functions
RESET
Figure 16-8. Port B I/O Circuit
SCTxD
Output
PTC6
6
(2)
SPSCK
PTC5
5
Accesses to DDRB
DDRBx
PTBx
Read/Write
DDRB[7:0]
DDRB[7:0]
# PTB3–PTB0 are open-drain pins when configured as outputs.
PTB7–PTB4 have schmitt trigger inputs.
Unaffected by reset
PTC4
SS
4
PTC3
MOSI
3
PTB[7:0]
Read
Pin
Accesses to PTB
PTC2
MISO
2
PTB[7:0]
PTB[7:0]
PTC1
Write
1
PTBx
(3)
#
PTC0
IRQ2
Bit 0
Port C
265
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