MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 226

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Serial Peripheral Interface Module (SPI)
13.12.5 CGND (Clock Ground)
CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. It
is internally connected to V
13.13 I/O Registers
Three registers control and monitor SPI operation:
13.13.1 SPI Control Register
SPRIE — SPI Receiver Interrupt Enable Bit
SPMSTR — SPI Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
224
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•
•
•
•
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This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See
Figure 13-4
identical CPOL values. Reset clears the CPOL bit.
This read/write bit controls the timing relationship between the serial clock and SPI data. (See
Figure 13-4
identical CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1
between bytes. (See
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
1 = Master mode
0 = Slave mode
SPI control register (SPCR)
SPI status and control register (SPSCR)
SPI data register (SPDR)
Enables SPI module interrupt requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
Enables the SPI module
Address:
and
and
Reset:
Read:
Write:
Figure
Figure
SPRIE
$0010
Bit 7
Figure
0
13-6.) To transmit data between SPI modules, the SPI modules must have
13-6.) To transmit data between SPI modules, the SPI modules must have
SS
Figure 13-13. SPI Control Register (SPCR)
as shown in
= Unimplemented
13-12.) Reset sets the CPHA bit.
R
6
0
MC68HC908AP Family Data Sheet, Rev. 4
SPMSTR
5
1
Table
13-1.
CPOL
4
0
CPHA
R
3
1
= Reserved
SPWOM
2
0
SPE
1
0
Freescale Semiconductor
SPTIE
Bit 0
0