MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 138

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Timer Interface Module (TIM)
9.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register
select the TIM clock source.
9.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
9.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU
interrupt requests.
9.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in
Output
the new value over the old value currently in the TIM channel registers.
138
Addr.
$002F
$0030
$0031
$0032
$0033
$0034
$0035
Compare. The pulses are unbuffered because changing the output compare value requires writing
TIM2 Channel 0 Status
TIM2 Channel 1 Status
TIM2 Counter Modulo
and Control Register
and Control Register
Register Name
TIM2 Channel 0
TIM2 Channel 0
TIM2 Channel 1
TIM2 Channel 1
Register High
Register High
Register Low
Register Low
Register Low
(T2MODL)
(T2CH0H)
(T2CH1H)
(T2CH0L)
(T2CH1L)
(T2SC0)
(T2SC1)
Figure 9-2. TIM I/O Register Summary (Sheet 2 of 2)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
MC68HC908AP Family Data Sheet, Rev. 4
CH0F
Bit 15
CH1F
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
1
0
0
0
0
= Unimplemented
CH0IE
CH1IE
14
14
6
6
1
0
6
0
6
MS0B
13
13
5
5
1
0
5
0
0
5
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
MS0A
MS1A
12
12
4
4
1
0
4
0
4
ELS0B
ELS1B
11
11
3
3
1
0
3
0
3
ELS0A
ELS1A
10
10
2
2
1
0
2
0
2
Freescale Semiconductor
TOV0
TOV1
1
1
1
0
9
1
0
9
1
9.4.3
CH0MAX
CH1MAX
Bit 0
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
1
0
0