PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 108

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
sampled on the rising clock edge where EOM is sampled
asserted.
The message passing mode view of the VI MMIO regis-
ters is shown in
in
operation in raw-capture mode, except that transitions to
another active buffer occur upon receipt of EOM rather
than on buffer full. OVERRUN is raised if the second
buffer receives a complete message before a new buffer
is assigned by the DSPCPU.
OVERFLOW is raised if a buffer is full and no EOM has
been received. If enabled, it causes a DSPCPU interrupt.
Since digital interconnection between devices is reliable,
overflow is indicative of a protocol error between the two
PNX1300s involved in the exchange (failure to agree on
message size). Detection of overflow leads to total halt of
capture of this message. Capture resumes in the next
buffer upon receipt of the next START event on
VI_DATA[8]. The OVERFLOW flag is sticky and can only
be cleared by writing a ‘1’ to ACK_OVF.
6-12
Figure 6-18. VI message passing mode major states.
Figure 6-17. VI message passing signal example.
Figure
VI_DATA[7:0]
VI_DATA[8]
VI_DATA[9]
6-18. The operation is almost identical to the
VI_CLK
ACK2
Figure
PRELIMINARY SPECIFICATION
6-15. The major states are shown
RESET
No EOM ⇒ raise OVERFLOW*
No EOM ⇒ raise OVERFLOW*
message
Start of
(
(
See text in
See text in
XX
D0
Section
Section
6.6)
6.6)
D1
ACTIVE = BUF1
ACTIVE = BUF2
ACTIVE = BUF2
ACTIVE = BUF1
BUF1FULL
BUF2FULL
ACK1
EOM
EOM
D2
D3
Highway bandwidth error behavior in message passing
mode is identical to that of raw mode.
6.6.1
PNX1300 offers a new mode where the VI_DVALID pin
does not control the sampling of the VI_DATA[9:8] pins.
These pins are used for END and START of a message.
This new mode is controlled by a new field, VALID, in the
VI_CLOCK MMIO register. The default value after RE-
SET is ‘0’.
When VI_CLOCK.VALID is set to ‘0’ (the RESET value)
then PNX1300 behaves as in TM-1300. In this case the
START and END of messages are sampled only if the
VI_DVALID pin is HIGH.
When VI_CLOCK.VALID is set to ‘1’ then PNX1300 acti-
vates the new behavior. In this case the START and END
of messages are always sampled independently of the
state of the VI_DVALID pin.
VI_CLOCK.VALID cannot be read back, therefore it al-
ways read 0.
D4
* OVERRUN and OVERFLOW are sticky flags. They are set,
but do not affect operation. They can only be cleared by soft-
ware, by writing a ‘1’ to ACK_OVR or ACK_OVF.
(See text in
VI_DVALID in Message Passing Mode
D5
Section
raise OVERRUN*
BUF1FULL
BUF2FULL
6.6)
D6
Philips Semiconductors
message
End of
D7
XX
XX