PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 285

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PCI-XIO External I/O Bus
22.1
In this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The PNX1300 PCI-XIO bus allows glueless connection
to PCI peripherals, 8-bit microprocessor peripherals and
8-bit memory devices. All these device types can be in-
termixed in a single PNX1300 system.
The PCI-XIO bus provides the following features:
• All PCI 2.1 features (32-bit, 33 MHz)
• Simple, non-multiplexed, 8-bit data, 24-bit address
• Glueless connection to ROM, EPROM, flash
• Programmable internal or external bus clock source
• 0-7 programmable wait states for XIO devices
• Support for single byte read, single byte write, DMA
• The 16 MB of XIO device space is visible as 16
22.1.1
The XIO logic that implements the protocol for 8-bit de-
vices appears as a on-chip PCI target device to the rest
of the PNX1300. It only responds when it is addressed by
the PNX1300 as initiator and never responds to external
PCI masters. When it is addressed by the PNX1300 as
an initiator, it responds to the PNX1300 PCI BIU as a nor-
mal slave device, activating PCI_DEVSEL#.
The XIO logic serves as a bridge between the PCI bus
and XIO devices such as ROMs, flash EPROMs and I/O
device chips. The PNX1300 addresses XIO devices on
the PCI-XIO bus in the same way as registers or memory
in any other PCI slave device. The XIO logic supplies the
PCI_TRDY# signals to the PCI bus and also supplies the
chip-select, read, write and data-strobe signals to XIO
devices attached to the PCI-XIO Bus. A conceptual only
block diagram of the PCI-XIO Bus is shown in
Figure
signals and PCI_C/BE#[0:3] signals for both PCI and
XIO devices, as shown in
The XIO logic is activated when the Enable bit in the
XIO_CTL register is asserted and whenever the
PNX1300 (as initiator) addresses the PCI-XIO bus ad-
dress range, as defined by a 6-bit address field in the XIO
XIO bus with control signals for 68K and x86 style
devices
EEPROM, UARTs, SRAM, etc.
read or DMA write
MWords (64 MBytes) in the DSPCPU memory map
22-2. The real hardware uses the PCI_AD[0:30]
SUMMARY FUNCTIONALITY
Description
Figure
22-3.
Bus Control Register. This 6-bit field defines the 6 most
significant bits of the XIO Bus address space. When the
PNX1300 sends out an address as an initiator, the upper
6 bits of the address are compared with this field. If they
match, the PCI-XIO bus logic is activated. The
PCI_INTB# output is asserted to indicate that the PCI-
XIO Bus is active. It becomes active at PCI data phase
time. When XIO is enabled, the PCI_INTB# signal be-
comes dedicated as XIO bus chip-select, and turns from
an open-drain output into a normal logic output.
PCI_INTB# serves as a global chip select for all XIO Bus
chips. When XIO is disabled, PCI_INTB# is available for
PCI-specific use or as a general purpose software I/O pin
with open-drain behavior as in TM-1000.
The Address field bits in the XIO Bus Control register
serve as a base address register in PCI terms. The XIO
Bus Control register is not a PCI configuration register. It
does not need to be a PCI configuration register because
the PCI-XIO Bus can only be addressed by the
PNX1300. It will not respond to requests by any other ex-
ternal PCI device.
When the XIO-PCI Bus controller logic is activated, it
generates PCI_DEVSEL# as a response to the PCI bus.
When PCI_IRDY# has been received from the BIU, it as-
serts an external PCI_INTB# signal as the global chip se-
lect. It also reconfigures the PCI address/data pins for 8-
bit byte transfers. When the PCI-XIO Bus is active, the
lower 24 bits of the external 32-bit PCI bus are used to
output a 24-bit address for all transfers, read or write.
The upper 8 bits of the external PCI bus are unchanged
and transfer data normally. This is shown in
The 24-bit address on the XIO Bus pins is the word ad-
dress for the PCI transfer, which is the lower 26 bits of
the PCI transfer address with the two least significant bits
ignored. One word is transferred to or from the PCI bus
for each byte read or written on the XIO bus. In writes to
the XIO bus, a 32-bit word is transferred from the PCI
BIU to the XIO Bus controller, but the lower 24 bits and
the PCI byte enables are ignored. In reads from the PCI
bus, a 32-bit word is transferred from the XIO Bus con-
troller to the PCI BIU with the data in the upper 8 bits and
the 24-bit address in the lower 24 bits. Note that the 24-
bit address returned in a read is the lower 26 bits of the
PCI transfer address with the two least significant bits
truncated. For example, a PCI transfer address of 44
hexadecimal would return a value of 11 hexadecimal as
the lower 24 bits of the 32-bit data in a read. The 24-bit
XIO Bus address is generated by an address counter in
the XIO Bus controller. This counter is loaded with the
PCI word address at PCI frame time at the start of the
PRELIMINARY SPECIFICATION
Chapter 22
By David Wyland
Figure
22-3.
22-1