PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 138

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
8.3
Figure 8-1
AI unit. At the heart of the clock system is a square wave
DDS (Direct Digital Synthesizer). The DDS can be pro-
grammed to emit frequencies from approx. 1 Hz to 40
MHz with a resolution of better than 0.3 Hz.
The output of the DDS is always sent on the AI_OSCLK
output pin. This output is intended to be used as the
256f
quency crystal for oversampling A/D converters, such as
the Philips SAA7366T, or Analog Devices AD1847.
The PNX1300 AI DDS frequency is set by writing to the
FREQUENCY MMIO register. The programmer can
change the FREQUENCY setting dynamically, so as to
adjust the input sampling rate to track an application de-
pendent master reference.
Depending on bit 31 (MSB), the DDS runs in one of two
modes:
• bit 31 = 1 (PNX1300 improved mode)
• bit 31 = 0 (TM-1000 compatibility mode)
8.3.1
In improved mode, a high quality, low-jitter AI_OSCLK is
generated. The setting of the FREQUENCY register to
accomplish a given AI_OSCLK frequency is given by:
This mode, and the above formula, should be used for all
new software development on PNX1300. It is not avail-
able on TM-1000.
In the improved mode the DDS synthesizer maximum jit-
ter can be computed as follows:
Example of jitter values can be found in
8-2
Figure 8-1. AI clock system and I/O interface.
FREQUENCY
s
AI_OSCLK
jitter
or 384f
AI_SCK
AI_WS
CLOCK SYSTEM
AI_SD
PNX1300 Improved Mode
illustrates the different clock capabilities of the
(e.g. 256×f
(e.g. 64×f
=
s
system clock source instead of a fixed fre-
---------------------------- -
9 f
⋅
s
s
)
DSPCPU
)
1
=
PRELIMINARY SPECIFICATION
2
31
Serial To Parallel Converter
+
f
----------------------------- -
9 f
OSCLK
⋅
DSPCPU
div N+1
div N+1
SER_MASTER
⋅
2
Table
32
8-2.
8
7
16
16
WSDIV
SCKDIV
LEFT[15:0]
RIGHT[15:0]
sample_clock
Table 8-2. Jitter values for common DSPCPU MHz
8.3.2
TM-1000 compatibility mode is provided so that TM-1000
software runs without changes. It should NOT be used
for new PNX1300 software development. TM-1000
mode is automatically entered whenever FREQUEN-
CY[31] = 0. In TM-1000 mode, AI_OSCLK frequency is
set as follows:
8.4
AI_SCK and AI_WS can be configured as input or out-
put, as determined by the SER_MASTER control field.
As output, AI_SCK is a divider of the DDS output fre-
quency. Whether input or output, the AI_SCK pin signal
is used as the bit clock for serial-parallel conversion.
If set as output, AI_WS can similarly be programmed us-
ing WSDIV to control the serial frame length from 1 to
512 bits.
The preferred application of the clock system options is
to use AI_OSCLK as A/D master clock, and let the A/D
converter be timing master over the serial interface
(SER_MASTER=0).
In case an external codec (e.g. the AD1847 or CS4218)
is used for common audio I/O, it may not be possible to
independently control the A/D and D/A system clocks. In
that case it is recommended that the Audio Out (AO) unit
9 × DSPCPUCLK
f
DSPCPU
(MHz)
f
143
166
AISCK
0
0
FREQUENCY
CLOCK SYSTEM OPERATION
TM-1000 Compatibility Mode
=
31
--------------------------------- -
SCKDIV
f
AI
(nSec)
0.777
0.669
OSCLK
jitter
+
1
=
Square Wave DDS
FREQUENCY
Philips Semiconductors
f
----------------------------- -
3 f
OSCLK
⋅
f
DSPCPU
(MHz)
DSPCPU
180
200
SCKDIV
⋅
2
32
∈
[ ,
0 255
(nSec)
0.617
0.555
jitter
]
0