PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 248

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
ADDRESS must be programmed to contain the 7 bits of
the desired slave address
The DIRECTION bitfield controls read/write operation on
the
• DIRECTION = 0 –> I
• DIRECTION = 1 –> I
The COUNT field must contain the desired bytecount for
the current transfer. The COUNT field will decrement by
one for each data byte transferred across
maining bytecount for the current transfer can be read
from the COUNT field at any time. Note that the
DSPCPU must refrain from rewriting the IIC_AR register
until the current transfer completes to avoid corrupting
the bytecount or address fields.
Note: For writes, the byte count decrements before the
byte is actually transferred over the I
the last byte is saved in an internal register and the
DSPCPU can write a new word when COUNT = 0.
16-2
Figure 16-2. I
MMIO_base
0x10 3400
0x10 340C
0x10 3404
0x10 3408
I
offset:
2
C
interface. The bit definition is:
IIC_SR (r/o)
IIC_AR (r/w)
IIC_CR (r/w)
IIC_DR (r/w)
2
C registers
GD_IEN
SDNACK_IEN
SANACK_IEN
F_IEN
SDA_STAT
SCL_STAT
GDI
SDNACKI
SANACKI
PRELIMINARY SPECIFICATION
FI
2
2
C write
C read
DIRECTION
31
31
31
31
CLRGDI
CLRSANACKI
CLRSDNACKI
ADDRESS
CLRFI
BYTE3
27
27
27
27
2
DIRECTION
C bus. However,
reserved
STATE
I
2
C
. The re-
23
23
23
23
reserved
BYTE2
19
19
19
19
16.4.2
The IIC_DR register contains the actual data transferred
during
data transfer will be initiated when data is written to this
register. Transmission will begin with the transfer of the
address byte in the IIC_AR register followed by the data
bytes that were written to the IIC_DR register, byte3 first
and byte0 last. The
transmit data to be written to the IIC_DR until the transfer
bytecount COUNT in the IIC_AR register is reached.
In master receive operation, one or more data bytes re-
ceived are placed in the IIC_DR register by the
face. Data bytes received are loaded into the IIC_DR
register starting with byte3, then byte2, byte1 and byte0.:
The number of bytes the DSPCPU requests for a transfer
is written into the COUNT bitfield of the IIC_AR register.
The transfer completes when the
the number of bytes indicated by the COUNT bitfield of
the IIC_AR register.
I
2
SW_MODE_EN
C
15
15
15
15
IIC_DR Register
operation. For a master transmit operation,
SDA_OUT
SCL_OUT
ENABLE
COUNT
RBC
BYTE1
I
11
2
11
11
11
C
interface will interrupt for more
Philips Semiconductors
7
7
7
7
I
2
C
interface receives
BYTE0
3
3
3
3
I
2
C
inter-
0
0
0
0