PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 256

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
17.3.1
Figure 17-2
purpose I/O pins. The SSI_IO1 and SSI_IO2 external
pins may be used as general purpose I/O by proper con-
figuration of the SSI_CTL register, or they may be used
as transmit clock input and as transmit framing signal in-
put or output. The SSI_CTL.IO1 and SSI_CTL.IO2 Mode
Select fields control the direction and functionality of
these two pins.
17-2
Figure 17-1. The SSI interface block diagram
Figure 17-2. I/O block diagram
SSI_RxDATA
SSI_RxCLK
SSI_RxFSX
SSI_IO1
SSI_IO1
SSI_IO2
General Purpose I/O
internal TxFSX
SSI_RxFSX
illustrates the functionality of the general
SSI_IO2
PRELIMINARY SPECIFICATION
IO1[1:0]=00
IO1[1:0]=01
IO2[1:0] = 10
IO2[1:0] = 10
internal TxFSX
Frame Synchronization
WIO2
SSI Receive
I/O Control
Block
Block
Block
MUX
2:1
WIO1
RIO1
IO2[1:0] = 00
IO2[1:0] = 00
IO2[1:0] = 11
IO2[1:0] = 11
SSI_RxCLK
TxCLK
TxFSX
SSI_IO1
A hardware reset or a software reset of the transmitter
through SSI_CTL.TXR command sets the SSI_CTL.IO1
and SSI_CTL.O2 fields to 11b, a conflict-free initial pin
state.Table 17-2
SSI_IO1,
on SSI_IO2. Note: If SSI_IO1 is not selected as transmit
clock input, the transmit clock is taken from the receive
clock signal instead. If SSI_IO2 is not selected as trans-
mit framing signal input or output, the transmit framing
signal is taken from the receive framing signal instead.
MUX
MUX
2:1
2:1
SSI Transmit
Table 17-3
IO1[1:0]=10
IO1[1:0]=10
Block
IO2[0] = 0
shows the effect of SSI_CTL.IO1 on pin
TxFSX
shows the effect of SSI_CTL.IO2
MUX
2:1
Philips Semiconductors
TxCLK
IO2[0] = 1
SSI_TxDATA
RIO2
SSI_IO2