PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 118

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
Figure 7-15. EVO VO_IO1 timing in FIELD_SYNC mode.
The horizontal timing signal VO_IO1, shown in
Figure
terval. It is active low from the EAV code at the start of
the line to the SAV code at the start of active video for the
line.
7.10
In Genlock mode, the EVO is not synchronization master
but receives frame timing signals on VO_IO2. The EVO
operates in Genlock mode when SYNC_MASTER = 0,
EVO_CTL. EVO_ENABLE = 1 and EVO_CTL. GEN-
LOCK = 1.
The active edge can be programmed using the VO_CTL.
VO_IO2_POS bit. The initial transition of the frame tim-
ing signal on VO_IO2 causes the Frame Line Counter to
be set to the value in VO_FRAME. FRAME_PRESET.
After reaching FRAME_LENGTH, the Frame Line
Counter starts counting again from 1.
EVO_SLVDLY. SLAVE_DLY is typically used to com-
pensate for any delay in the frame timing source or inter-
nal pipeline synchronization anywhere in a line. Internal-
ly, the active edge of VO_IO2 is delayed by SLAVE_DLY
VO_CLK clock cycles. Typically, it will allow FRAME_
PRESET to be loaded at the beginning of a new line.
With
FRAME_PRESET loaded, the PNX1300 can generate
frames totally synchronized with the active edge of
VO_IO2. All the internal MMIO registers (except of
7-8
Figure 7-14. EVO VO_IO2 timing in FIELD_SYNC mode.
Vertical
Sync
VO_IO2
NTSC
PAL
7-15, corresponds to the horizontal-blanking in-
Video
Lines
GENLOCK MODE
correct
1
4
Image Data
Blanking
values
VO_IO1
PRELIMINARY SPECIFICATION
22
19 20
EAV
Blanking
of
23
Active Video
Field 1
SAV
One Line
SLAVE_DLY
Field Width, Pixels
Image Line: Image Width
263 264
310 311
Image Width, Pixels
and
Blanking
One Frame
312 313
265 266
course VO_CTL) should be programmed with the same
values as for SYNC_MASTER mode. See
In Genlock mode, the EVO is free-running according to
the values programmed in its internal registers before the
initial VO_IO2 active edge. Just after receiving the active
edge that will synchronize the EVO, output values may
be erroneous for several VO_CLK cycles, but it is guar-
anteed that the next frame will be correct.
After the first synchronizing edge, if the next one hap-
pens according to the values programmed in the EVO
MMIO registers, no change will appear in the output tim-
ing of the EVO. If the active edge of VO_IO2 does not
match the programmed value, a new synchronization
phase is performed.
Typically, this is programmed as follows: SLAVE_DLY is
loaded with the number of clock cycles for one video line
minus the number of delay cycles used by the EVO to
synchronize itself. FRAME_PRESET is programmed
with the value 2. With this programming, the active edge
of VO_IO2 will happen just before the first byte (pream-
ble) of the first line.
The first active edge of VO_IO2 is delayed internally by
SLAVE_DLY VO_CLK cycles so that it appears internally
just before the start of the second line minus the internal
EVO pipeline delay. After this internal pipeline delay, the
line counter is loaded by FRAME_PRESET, (‘2’), and the
EVO starts sending data for line 2.
For the next frame, if the internal EVO programming
matches the VO_IO2 timing, the EVO will appear to start
Blanking
Blanking
EAV
335 336
282
Field 2
283
Active Video
Philips Semiconductors
525
623 624 625 1
Blanking
1
Figure
3
7-16.
4