PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 234

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
interpolation is used. (See
This is shown in
14.6.10 Vertical Filter - SDRAM to SDRAM
This routine performs vertical scaling and filtering of one
component (Y, U or V) of an N x M image from one loca-
tion in SDRAM to another.
14.6.10.1 Algorithms
The routine reads image data from SDRAM using the Y
address counter, scales and filters the data in the vertical
direction, and writes it back to the SDRAM using the Z
address counter. The 5-tap filter scales and filters the da-
ta. The U LSB register is used as the scaling coefficient
register. The U LSB Increment value supplied by the pa-
rameter table determines the scaling. Lines at the top
and bottom of the image are mirrored to provide the extra
line data needed by the 5-tap filter.
Figure 14-19. Vertical filter parameter table
14-24
Input image start address
U counter
Start fraction
Fraction increment
Input image height
Output image start address
Control
Output image height
Figure 14-18. Normal vs. Large down scaling for scale factor = 5.0
Input Pixels
Output Pixels
Input Pixels
Output Pixels
Upper 2 bytes
Figure
Parameter Word
0
0
PRELIMINARY SPECIFICATION
1 2 3 4 5 6 7 8 9 10 11 12 13 1415 16 17 18 1920
1 2 3 4 5 6 7 8 9 10 11 12 13 1415 16 17 18 19 20
14-18.
Input image
Line offset
Integer increment
Input image width
Output image
Line offset
Output Image Width
Section 14.5.2,
Lower 2 bytes
“Filtering”)
P2N = F(10, 11, 12, 13, 14)
Normal Down Scaling
P2L = F(2, 7, 12, 17, 22)
Large Down Scaling
Starting value: may be 0.5, etc. for interspersed convert;
Line offset from X0Y0 to X0Y1
Increment value for U = 1/scale factor
Height and width in input lines and pixels
Start address of X0Y0 (byte address)
Control Word; Line offset from X0Y0 to X0Y1
Start address of X0Y0 (byte address)
Height and width in output lines and pixels
The routine reads and writes data in 64-byte (one
SDRAM block) columns of pixels until the entire image is
transferred. For each column, line segments of 64 pixels
are processed until the entire column has been pro-
cessed. Each 64-pixel line segment generated requires
five vertically adjacent 64-pixel line segments as input to
the 5-tap filter. The routine processes the image in pixel
columns to eliminate redundant read of input pixel data:
each new line segment typically requires reading only
one new 64 byte line segment.
The routine processes data in 64-pixel blocks, corre-
sponding to the input block buffer sizes. Five buffers are
used in processing the current line segment, while the
sixth buffer reads in the next line segment in overlap with
current processing.
14.6.10.2 Parameter table
The parameter table, as shown in
the input and output starting addresses and offsets, the
image height in lines and width in pixels, and the scale
factor.
21 22 23 24 25
Description
Philips Semiconductors
Figure
14-19, supplies