PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 463

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
st32d
SYNTAX
FUNCTION
DESCRIPTION
arguments. (Note: pseudo operations cannot be used in assembly files.)
The d value is an opcode modifier, must be in the range –256 and 252 inclusive, and must be a multiple of 4. This
store operation is performed as little-endian or big-endian depending on the current setting of the bytesex bit in the
PCSW.
undefined, and the MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if the TRPMSE
(TRaP on Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the next
interruptible jump.
memory operations is undefined). The state of the BSX bit in the PCSW has no effect on MMIO access by
modification of the addressed memory locations (and the modification of cache if the locations are cacheable). If the
LSB of rguard is 1, the store takes effect. If the LSB of rguard is 0, st32d has no side effects whatever; in particular,
the LRU and other status bits in the data cache are not affected.
EXAMPLES
A-165
r10 = 0xcfc, r80 = 0x44332211
r50 = 0, r20 = 0xd0b,
r70 = 0xaabbccdd
r60 = 1, r30 = 0xd0c,
r70 = 0xaabbccdd
The
The
If
The
The
[ IF rguard ] st32d(d) rsrc1 rsrc2
if rguard then {
}
st32d
if PCSW.bytesex = LITTLE_ENDIAN then
else
mem[rsrc1 + d + (3 ⊕ bs)] ← rsrc2<7:0>
mem[rsrc1 + d + (2 ⊕ bs)] ← rsrc2<15:8>
mem[rsrc1 + d + (1 ⊕ bs)] ← rsrc2<23:16>
mem[rsrc1 + d + (0 ⊕ bs)] ← rsrc2<31:24>
st32d
st32d
st32d
bs ← 3
bs ← 0
st32d
Initial Values
is misaligned (the memory address computed by rsrc1 + d is not a multiple of 4), the result of
operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bit
operation stores all 32 bits of rsrc2 into the memory locations pointed to by the address in rsrc1 + d.
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
operation is a pseudo operation transformed by the scheduler into an
PRELIMINARY SPECIFICATION
st32d(4) r10 r80
IF r50 st32d(–8) r20 r70
IF r60 st32d(–8) r30 r70
Operation
32-bit store with displacement
[0xd00] ← 0x44, [0xd01] ← 0x33,
[0xd02] ← 0x22, [0xd03] ← 0x11
no change, since guard is false
[0xd04] ← 0xaa, [0xd05] ← 0xbb,
[0xd06] ← 0xcc, [0xd07] ← 0xdd
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
h_st32d st32 st16 st16d
Philips Semiconductors
pseudo-op for h_st32d
h_st32d
ATTRIBUTES
SEE ALSO
st8 st8d
Result
with the same
–256..252 by 4
st32d
dmem
7 bits
st32d
4, 5
n/a
31
2
.
is