PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 170

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
• The initiator asserted perr# or detected it asserted by
Table 11-3. Status register fields
DEVSEL (Device select timing). This read-only field
defines the slowest timing that will be used for the
devsel# signal when PNX1300 is a target on the PCI bus.
Table 11-4
ings. These bits are hardwired to ‘01’ to indicate that
Table 11-4. DEVSEL encodings
PNX1300 uses a ‘medium’ devsel# timing.
STA (Signaled target abort). PNX1300’s PCI interface
sets this bit when it is a target device and aborts a trans-
action.
RTA (Receive target abort). PNX1300’s PCI interface
sets this bit when it is the initiating device and the trans-
action is aborted by the target device. (All initiating devic-
es must implement this bit.)
RMA (Receive master abort). PNX1300’s PCI interface
sets this bit when it is the initiating device and aborts a
transaction (except when the transaction is a special cy-
cle). (All initiating devices must implement this bit.)
SSE (Signaled system error). PNX1300’s PCI interface
sets this bit when it asserts the serr# signal. (PNX1300
Figure 11-5. Class-code register format.
11-6
Reserved Writes ignored; reads return 0
66M
UDF
FBC
DPD
DEVSEL
STA
RTA
RMA
SSE
DPE
Field
the target (during a write cycle).
DEVSEL
00
01
10
11
PCI bus speed (hardwired to 0 ⇒ 33-MHz)
User-definable features (hardwired to 0 ⇒ none)
Fast back-to-back capable (hardwired to 0 ⇒
unsupported)
Data parity detected
devsel# signal timing (hardwired to 1 ⇒ ‘medium’)
Signaled target abort
Receive target abort
Receive master abort
Signaled system error
Detected parity error
shows the allowable encodings and mean-
Class Code
PRELIMINARY SPECIFICATION
23
Characteristics
Base Class Code
Reserved
Meaning
Medium
Slow
Fast
15
Subclass Code
can generate serr#, so this bit is implemented; devices
incapable of generating serr# need not implement SSE.)
DPE (Detected parity error). PNX1300’s PCI interface
sets this bit when it detects a parity error, even if parity
error handling is disabled. (The PAR bit in the command
register enables the handling of parity errors.)
11.5.5
The value in the Revision ID register is a read only value
chosen by the manufacturer to indicate product revi-
sions. For the PNX1300 product family, the two MSBs of
the revision ID indicate the fab where the part was man-
ufactured. The next two bits indicate an all-layer revision
number, and the 4 LSBs indicate metal layer revisions.
Each all-layer revision adds 0x10 to the revision ID and
resets the 4 LSBs to ‘0’. Non-pin or -function compatible
TriMedia devices will use the same Revision ID conven-
tion, but with a revised Device ID.
Table 11-5. Actual revision ID values
11.5.6
The value in the Class Code register is read-only. Sys-
tem software uses the Class Code register to identify the
generic function of the device, and in some cases, the
Class Code can specify a register-level programming in-
terface.
Class Code consists of three 1-byte fields as shown in
Figure
Code, broadly classifies the function of the device. The
value of the middle byte, Subclass Code, identifies the
function more specifically. The value of the lower byte
specifies a register-level programming interface so that
device-independent software can interact with the de-
vice. The meanings of the Base Class byte values are
shown in
The value of Base Class is hardwired to 0x04 since
PNX1300 is a multimedia device. Currently, there are no
specific register-level programming interfaces defined
for multimedia devices.
Table 11-7
vices. PNX1300 is both a video and audio multimedia de-
vice, so its subclass value is hardwired to 0x80.
Value (hex)
0x80
0x81
0x82
0x83
11-5. The value of the upper byte, Base Class
Table
Revision ID Register
Class Code Register
lists the defined subclasses of multimedia de-
TM-1300
TM-1300
TM-1300
PNX1300/01/02/11 3nd metal revision - tm1f-
1.3
11-6.
7
Programming Interface
original mask - tm1f-1.0
1st metal revision - tm1f-1.1
2nd metal revision - tm1f-1.2
Product description
Philips Semiconductors
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