PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 224

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
the output line is half way between Y
contains a set of 5 filter parameter RAMs, one for each
coefficient. The 5 most significant LSBs from the counter
select the filter coefficients which will generate the cor-
rect value for the output pixel at the relative offset from
0.0 indicated by the LSBs.
For down scaling, the increment factor will be greater
than one. If the increment factor is 2.0, two new blocks
will have to be loaded before starting the next vertical fil-
ter pass. If the increment factor is 5 or greater, all five
blocks must be loaded. The number of blocks to be load-
ed for the next line is equal to the integer increment value
plus carry out from the LSB portion of the U Counter in-
crement.
Note that the LSB adder carry out is available before the
U Counter has been updated. This allows the current U
Counter value LSB bits to be used for the filter coeffi-
cients while using the carry out for the next value to pre-
dict how many blocks to fetch. The integer value from the
U increment value plus the carry in from the LSB portion
of the Increment adder is the number of blocks to be
loaded. These blocks must be sequentially loaded (and
not skipped) so that the filter has the necessary 5 adja-
cent lines to perform the filtering. The contents of the in-
teger portion of the U Counter (updated after the add) are
not used.
14-14
Figure 14-14. ICP vertical scaling data flow block diagram
Block Address
to SDRAM
Block Count
to Microcode
SDRAM
Pixel Clock
Line Clock
PRELIMINARY SPECIFICATION
Yn+2 Buffer
Yn+1 Buffer
Yn+0 Buffer
Yn-1 Buffer
U Incr Integer
Yn-2 Buffer
Y Counter
U MSB Cntr
n
and Y
Byte Index
n+1
. The filter
Carry
U Incr Fraction
U LSB Reg
5-tap Filter
Only one new block can be loaded while the current line
is being processed. If two or more blocks are needed to
process the next line, load one in overlap. Wait until the
current line is done, then load the rest of the blocks. The
microprogram only has to make two decisions for the
next line: is the increment value ‘0’ or greater than ‘0’,
and if greater than ‘0’, is it greater than five. If it is ‘0’, do
nothing: you will reuse all five blocks. If it is 1-4, load the
next block. If it is five or more, calculate the address of
the first block -- by adding N times the address offset to
the Y counter -- and fetch it.
When a new block is loaded and it is time to process the
next line, the block which was Y
Y blocks, in effect, shift up one line as you scan down the
image. This shifting action is implemented by shifting the
block select codes in the Filter Source Select Register
(FSSR). The FSSR contains six 3-bit register fields.
These 3-bit fields are rotated by a shift command to the
FSSR. The output of five of the FSSR fields go to the in-
put multiplexer, which selects the next block combination
and sends it to the filter. The output of the sixth field is the
free block to be filled for the next line while the current
line is being processed. The select code is also the block
code (0 to 5), so the free block is identified by its block
code in the FSSR. The FSSR codes for the six cases of
vertical filtering are shown in
Filter Source Select
U LSBs
6 In x 5 Out
Multiplexer
Z Counter
Output
Pixel clock
Philips Semiconductors
Table
FSSR
n+2
14-4.
becomes Y
n+1
. The