PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 519

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

Table C-4. BIU.SE bit usage in processing data in
BIU unit
Philips Semiconductors
Table C-3. Big Endian data format in the PNX1300 DSPCPU register, highway, SDRAM memory, PCI bus, host
memory, and host CPU register
C.4.2
It is assumed that the instruction cache always operates
in Little Endian regardless of the host and PNX1300 en-
dian-ness. Instruction cache does not use the PCSW’s
byte sex bit (BSX). The compiler supports the loading of
instructions in memory differently for Big Endian and Lit-
tle Endian modes.
C.4.3
The PNX1300 highway bus and the PCI bus are address
invariant buses, i.e. a data corresponding to address
zero is always transferred through the byte-zero line re-
gardless of the endian-ness. The address-invariant na-
ture of the PCI and the highway buses allows data to be
transferred from/to PCI bus directly to/from SDRAM with-
out byte swapping in either Big or Little Endian mode The
byte swapping of data for Big Endian mode is performed
by the data cache unit. However, MMIO data does not go
through the byte swapper in the Data cache. This results
in using a byte-swapper in the BIU to byte-swap the
MMIO data in Big Endian mode.
The PNX1300 BIU has a separate byte sex (SE, Swap
Enabled) flag defined in its control register (BIU_CTL).
This byte-sex flag must be set by the software, i.e. MMIO
write operation from the host CPU. This byte-sex flag is
used only for MMIO data accesses and none of the
MMIO data accesses is affected by this SE flag.
4
cesses from the DSPCPU and host CPU and the non
MMIO data accesses from any source.
BIU.SE
PCSW-
value
value
shows the byte-swap logic that handles the MMIO ac-
BSX
0
1
0
0
0
0
0
0
0
Endian
Big
Little
Instruction Cache
PNX1300 PCI Interface Unit
Mode
Endian
Mode
Big
Big
Big
Big
Big
Big
Big
No byte-swap byte-swap
No byte-swap No byte-swap No byte-
DSPCPU
Data transaction
access
MMIO
Byte read/write
Byte read/write
Byte read/write
Byte read/write
from
Half-word r/w
Half-word r/w
Word r/w
type
access from
PCI side
MMIO
00001000
00001000
00001002
00001000
00001001
00001002
00001003
Address
Non MMIO
No byte-
swap
swap
Table C-
data
01020304
DSPCPU
xxxx0304
xxxx0304
xxxxxx04
xxxxxx04
xxxxxx04
xxxxxx04
msb lsb
register
Data in
The BIU has several special registers to handle memory,
PCI configuration, I/O and DMA accesses. It does not
byte-swap the I/O data from the special registers. The
data cache and software performs the necessary byte
swapping for this data.
When using PNX1300 in Little Endian-based systems,
the first transaction to the PNX1300 is to set the SE bit in
the BIU configuration register to avoid unnecessary soft-
ware byte-swapping in the host CPU for the subsequent
MMIO read/write accesses. The SE bit in the BIU_CTL
register controls the byte swapping of outgoing and in-
coming data from PCI bus. The default value of SE is ‘0’,
i.e the BIU byte-swaps the MMIO data including the write
operation to the BIU_CTL register. Software is required
to byte swap the BIU_CTL register value within the host
CPU before storing the value in BIU_CTL register. Once,
the BIU.SE bit has been set, no additional software byte-
swapping is required for further read/write operations to
any MMIO registers.
C.4.4
The input source data for the ICP unit might come from
different units such as Video In, the DSPCPU, PCI bus,
etc. via SDRAM. Data consistency needs to be main-
tained when the PNX1300 operates in Little or Big Endi-
an systems/mode. The ICP needs the capability to oper-
ate on the SDRAM as source data and SDRAM or PCI
as destination data in either Little or Big Endian mode.
Figure
trate the Big and Little Endian memory image format for
the image input format
ported image overlay formats.
The ICP can output the data to either the SDRAM or PCI
bus. RGB 8R and RGB 8A pixel formats are byte streams
and therefore do not require any byte swapping.
C-9
RGB-16 and YUV-4:2:2 pixel formats can be used to out-
put the pixels to PCI or SDRAM in both Endian modes.
Output formats are shown, respectively, in
Figure
cannot be used in Big Endian mode. Little Endian data
format is shown in
PRELIMINARY SPECIFICATION
Dcache/SDRAM/
Data in highway/
pictures the data format. RGB-24+α, RGB-15+α,
byte3
[31:24]
C-3,
C-5,
04030201
xxxx0403
0403xxxx
xxxxxx04
xxxx04xx
xx04xxxx
04xxxxxx
PCI-bus
Image Coprocessor (ICP)
Figure
Figure
byte0
[7:0]
C-8, and
Figure
C-4,
CPU register
Data in Host
msb
(Figure
Figure C-5
01020304
xxxx0304
xxxx0304
xxxxxx04
xxxxxx04
xxxxxx04
xxxxxx04
C-11.
Figure
lsb
C-3) and the three sup-
C-7. Packed RGB-24
and
byte0
[31:24]
Figure C-6
Data in host
Endian-ness
01020304
0304xxxx
xxxx0304
04xxxxxx
xx04xxxx
xxxx04xx
xxxxxx04
memory
Figure
byte3
[7:0]
Figure
illus-
C-4,
C-3