PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 269

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Table 18-1. JTAG instruction encoding
The JTAG instructions EXTEST, SAMPLE/PRELOAD,
and BYPASS are standard instructions and are not dis-
cussed here. The MACRO, BURNIN, and PASS_C_S in-
structions are used during hardware test mode, and are
also not discussed here. All other instructions are dis-
cussed in
18.3
Figure 18-2
from a host machine to a target TriMedia system and a
simplified block diagram of the TriMedia processor. The
JTAG Interface Module shown separately in the diagram
may be a PC add-on card such as PC-1149.1/100F
Boundary Scan Controller Board from Corelis Inc. or a
similar module connected to a PC serial or parallel port.
The JTAG interface module is necessary only for TriMe-
Figure 18-2. TriMedia system with JTAG test access
Encoding
10010
10011
10100
10101
01010
11110
01110
USING JTAG FOR PNX1300 DEBUG
Section 18.3
SEL_DATA_OUT
SEL_IFULL_IN
SEL_OFULL_OUT
SEL_JTAG_CTRL
MACRO
BURNIN
PASS_C_S
shows an overview of the JTAG access path
Instruction name
JTAG board
Connector
JTAG
controller
(such as a PC)
Host Machine
DSP
CPU
Select DATA_OUT register
Select IFULL_IN register
Select OFULL_OUT regis-
ter
Select JTAG_CTRL regis-
ter
Hardware test mode select
Private
Private
JTAG TAP (TCK, TMS, TDI, TDO)
D$
I$
Action
DATA Highway
MMIO
MMI
Serial or Parallel
Connection
dia systems that are not plugged into a PC. For PC-host-
ed TriMedia systems, the host based debugger front-end
can communicate with the target resident debug monitor
via the PCI bus.
The enhancements to the standard functionality of JTAG
test logic provides a handshake mechanism for transfer-
ring data to and from a TriMedia processor’s MMIO reg-
isters reserved for this purpose, for posting an interrupt,
and for resetting processor state. The actual interpreta-
tion of the contents of the MMIO registers is determined
by a software protocol used by the debug monitor run-
ning on the TriMedia processor and the debug front-end
running on a host machine.
The communication between a host computer and a tar-
get TriMedia system via JTAG requires, at a high level of
abstraction, the following components.
• A host computer with a serial or parallel inter-
• A JTAG interface module (hardware) that asyn-
PRELIMINARY SPECIFICATION
Scan Chain connecting possibly
other chips on board
face.
The host computer transfers data to and from the
JTAG interface module, preferably in word-parallel
fashion. A JTAG interface device driver is also
needed to access and modify the registers of the
JTAG interface module.
chronously transfers data to and from the host
computer.
The interface module synchronously transfers data to
and from the JTAG TAP on a TriMedia processor,
and supplies the test clock, TCK, and other signals to
JTAG Interface
May be a PC plug-in board
TriMedia Board
(SDRAM)
Main
Memory
JTAG Functional Specification
Module
18-3