PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 338

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Floating-point add
SYNTAX
FUNCTION
DESCRIPTION
precision floating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument is
denormalized, zero is substituted for the argument before computing the sum, and the IFZ flag in the PCSW is set. If
the result is denormalized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If
IEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the
flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
operation. The update of the PCSW exception flags occurs at the same time as rdest is written. If any other floating-
point compute operations update the PCSW at the same time, the net result in each exception flag is the logical OR of
all simultaneous updates ORed with the existing PCSW value for that exception flag.
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38)
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39)
r82 = 0x00c00000 (1.763241526e-38),
r83 = 0x80800000 (–1.175494351e-38)
r84 = 0x7f800000 (+INF),
r85 = 0xff800000 (–INF)
r70 = 0x7f7fffff (3.402823466e+38)
r80 = 0x00800000 (1.763241526e–38)
The
The
The
[ IF rguard ] fadd rsrc1 rsrc2 → rdest
if rguard then
fadd
faddflags
fadd
rdest ← (float)rsrc1 + (float)rsrc2
operation computes the sum rsrc1+rsrc2 and stores the result into rdest. All values are in IEEE single-
Initial Values
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
operation computes the exception flags that would result from an individual
fadd r60 r30 → r90
fadd r40 r60 → r95
IF r10 fadd r40 r80 → r100
IF r20 fadd r40 r80 → r110
fadd r40 r81 → r111
fadd r82 r83 → r112
fadd r84 r85 → r113
fadd r70 r70 → r120
fadd r80 r80 → r125
Operation
PRELIMINARY SPECIFICATION
PNX1300/01/02/11 DSPCPU Operations
r90 ← 0xc0000000 (–2.0)
r95 ← 0x00000000 (0.0)
no change, since guard is false
r110 ← 0x40400000 (3.0), INX flag set
r111 ← 0x40400000 (3.0), IFZ flag set
r112 ← 0x00000000 (0.0), OFZ, UNF,
INX flags set
r113 ← 0xffffffff (QNaN), INV flag set
r120 ← 0x7f800000 (+INF), OVF,
r125 ← 0x01000000 (2.350988702e–38)
INX flags set
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
faddflags iadd dspiadd
dspidualadd readpcsw
ATTRIBUTES
writepcsw
SEE ALSO
Result
fadd
fadd
.
writepcsw
causes an
fadd
falu
1, 4
No
22
—
2
3
A-40