PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 352

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Floating-point multiply
SYNTAX
FUNCTION
DESCRIPTION
precision floating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument is
denormalized, zero is substituted for the argument before computing the product, and the IFZ flag in the PCSW is set.
If the result is denormalized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If
IEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the
flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
operation. The update of the PCSW exception flags occurs at the same time as rdest is written. If any other floating-
point compute operations update the PCSW at the same time, the net result in each exception flag is the logical OR of
all simultaneous updates ORed with the existing PCSW value for that exception flag.
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38)
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38)
r41 = 0x3f000000 (0.5),
r80 = 0x00800000 (1.17549435e–38)
r42 = 0x7f800000 (+INF),
r43 = 0x0 (0.0)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39)
r82 = 0x00c00000 (1.763241526e–38),
r83 = 0x8080000 (–1.175494351e–38)
r84 = 0x7f800000 (+INF),
r85 = 0xff800000 (–INF)
r70 = 0x7f7fffff (3.402823466e+38)
r80 = 0x00800000 (1.763241526e–38)
The
The
The
[ IF rguard ] fmul rsrc1 rsrc2 → rdest
if rguard then
fmul
fmulflags
fmul
rdest ← (float)rsrc1 × (float)rsrc2
operation computes the product rsrc1×rsrc2 and stores the result into rdest. All values are in IEEE single-
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
Initial Values
operation computes the exception flags that would result from an individual
fmul r60 r30 → r90
fmul r40 r60 → r95
IF r10 fmul r40 r80 → r100
IF r20 fmul r40 r80 → r105
fmul r41 r80 → r110
fmul r42 r43 → r106
fmul r40 r81 → r111
fmul r82 r83 → r112
fmul r84 r85 → r113
fmul r70 r70 → r120
fmul r80 r80 → r125
Operation
PRELIMINARY SPECIFICATION
PNX1300/01/02/11 DSPCPU Operations
r90 ← 0xc0400000 (-3.0)
r95 ← 0xc1100000 (-9.0)
no change, since guard is false
r105 ← 0x1400000 (3.52648305e-38)
r110 ← 0x0, OFZ, UNF, INX flags set
r106 ← 0xffffffff (QNaN), INV flag set
r111 ← 0, IFZ flag set
r112 ← 0, UNF, INX flag set
r113 ← 0xff800000 (-INF)
r120 ← 0x7f800000, OVF, INX flags set
r125 ← 0, UNF, INX flag set
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dspidualmul fmulflags
readpcsw writepcsw
imul umul dspimul
ATTRIBUTES
SEE ALSO
Result
fmul
fmul
.
writepcsw
causes an
fmul
ifmul
2, 3
No
28
—
2
3
A-54