PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 273

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

On-Chip Semaphore Assist Device
19.1
In this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
PNX1300 has a simple MP semaphore-assist device. It
is a 32-bit register, accessible through MMIO by either
the local PNX1300 CPU or by any other CPU on PCI
through the aperture made available on PCI. The sema-
phore, SEM, is located at MMIO offset 0x10 0500.
SEM operation is as follows: each master in the system
constructs a personal nonzero 12 bit ID (see below). To
obtain the global semaphore, a master does the follow-
ing action:
write ID to SEM (use 32 bit store, with ID in 12 LSB)
retrieve SEM
if (SEM = ID) {
}
else “try again later, or loop back to write”
19.2
SEM is a 32-bit MMIO location. The 12 LSB consist of
storage flip-flops with surrounding logic, the 20 MSBs al-
ways return a ‘0’ when read.
SEM is RESET to ‘0’ by power up reset.
When SEM is written to, the storage flip-flops behave as
follows:
if (cur_content == 0)
else if (write_value == 0) new_content = 0;
/* ELSE NO ACTION ! */
19.3
A PNX1300 processor can construct a personal, nonzero
12-bit ID in a variety of ways. Below are some sugges-
tions.
PCI configspace PERSONALITY entry. Each PNX1300
receives a 16-bit PERSONALITY value from the EE-
PROM during boot. This PERSONALITY register is lo-
0x10 0500
“performs a short critical section action”
write 0 to SEM
OVERVIEW
SEM DEVICE SPECIFICATION
CONSTRUCTING A 12-BIT ID
31
00000000000000000000
(use 32 bit load, it returns 0x00000nnn)
new_content = write_value;
12 11
SEM
0
cated at offset 0x40 in configuration space. In a MP sys-
tem, some of the bits of PERSONALITY can be
individualized for each CPU involved, giving it a unique
2/3/4-bit ID, as needed given the maximum number of
CPUs in the design.
In the case of a host-assisted PNX1300 boot, the PCI
BIOS assigns a unique MMIO_BASE and DRAM_BASE
to every PNX1300. In particular, the 11 MSBs of each
MMIO_base are unique, since each MMIO aperture is 2
MB in size. These bits can be used as a personality ID.
Set bit 11 (MSB) to '1' to guarantee a nonzero ID#.
19.4
Each PNX1300 in the system adds a SEM device to the
mix. The intended use is to treat one of these SEM de-
vices as THE master semaphore in the system. Many
methods can be used to determine which SEM is master
SEM. Some examples below:
Each DSPCPU can use PCI configuration space access-
es to determine which other PNX1300s are present in
the system. Then, the PNX1300 with the lowest PER-
SONALITY number, or the lowest MMIO_base is chosen
as the PNX1300 containing the master semaphore.
19.5
To avoid contention on the master SEM device, it should
only be used for inter-processor semaphores. Processes
running on a single CPU can use regular memory to im-
plement synchronization primitives.
The critical section associated with SEM should be kept
as short as possible. Preferably, SEM should only be
used as the basis to make multiple memory-resident sim-
ple semaphores. In this case, the non-cacheable DRAM
area of each PNX1300 can be used to implement the
semaphore data structures efficiently.
As described here, SEM does not guarantee starvation-
free access to critical resources. Claiming of SEM is
purely stochastic. This should work fine as long as SEM
is not overloaded. Utmost care should be taken in SEM
access frequency and duration of the basic critical sec-
tions to keep the load conditions reasonable.
PRELIMINARY SPECIFICATION
WHICH SEM TO USE
USAGE NOTES
Chapter 19
19-1