PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 255

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

Synchronous Serial Interface
17.1
In this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The PNX1300 synchronous serial interface (SSI) unit in-
terfaces to an off-chip modem analog front end (MAFE)
subsystem, network terminator, ADC/DAC or codec
through a flexible bit-serial connection. The hardware
performs full-duplex serialization/deserialization of a bit
stream from any of these devices. Any such front end de-
vice connected must support transmitting, receiving of
data, and initialization via a synchronous serial interface.
Since the communication algorithm is implemented in
software by the PNX1300 DSPCPU and the analog inter-
face is off chip, a wide variety of modem, network and/or
FAX protocols may be supported.
The SSI hardware includes:
• A 16-bit receive shift register (RxSR), synchronized
• A 32-bit MMIO receive data register (SSI_RxDR) to
• 32-entry deep,16-bit wide receive buffer (RxFIFO), to
• A 16-bit transmit shift register (TxSR), synchronized
• A 32-bit MMIO transmit data register (SSI_TxDR) to
• 30-entry deep, 16-bit wide transmit buffer (TxFIFO),
• Transmit frame sync pulse generation logic
• Control and status logic
• Interrupt generation logic
The SSI unit is not a hiway bus master. All I/O is complet-
ed through DSPCPU MMIO cycles. FIFOs are used to in-
crease allowable interrupt response time and decrease
interrupt rate.
by an external receive frame synchronization pulse
(SSI_RxFSX) and clocked by an external clock
(RxCLK)
provide data access from the DSPCPU
buffer between the receive shift register (RxSR) and
MMIO receive data register (SSI_RxDR)
by an external or internal transmit frame synchroni-
zation pulse and clocked by an external clock (either
SSI_IO1 or SSI_RxCLK)
transmit data from the DSPCPU.
to buffer between the MMIO transmit data register
(SSI_TxDR) and transmit shift register (TxSR)
SYNCHRONOUS SERIAL INTERFACE
OVERVIEW
17.2
The external interface consists of the 6 pins described in
Table
Table 17-1. Synchronous serial interface pins
17.3
The main block diagram of the SSI unit is illustrated in
Figure
The I/O block is used for control of the I/O pins and for
selecting the transmit clock and transmit frame synchro-
nization signals.
The frame synchronization block can be used for gener-
ating an internal synchronization signal derived from re-
ceive clock input (SSI_RxCLK) or from an I/O pin
(SSI_IO1).
The SSI transmit block buffers and transmits the bits us-
ing the generated frame synchronization signal (TxFSX)
and the transmit clock. The transmit clock is either the re-
ceive clock or the clock present on SSI_IO1.
The SSI receive block receives and buffers the bits on
the SSI_RxDATA line, using the receive clock
(SSI_RxCLK) and the receive frame synchronization sig-
nal (SSI_RxFSX).
Each of the blocks will be described in detail in the next
subsections.
PRELIMINARY SPECIFICATION
SSI_RxCLK
SSI_RxFSX
SSI_RxDATA
SSI_TxDATA
SSI_IO1
SSI_IO2
Name
17-1.
17-1.
INTERFACE
BLOCK DIAGRAM
Type
I/O-5
I/O-5
OUT
IN-5
IN-5
IN-5
Serial interface clock signal; pro-
vided by an external communica-
tion device.
signal; provided by an external
communication device.
by the receive channel of an exter-
nal communication device.
Transmit serial data signal output.
Transmit clock input or general pur-
pose I/O pin.
signal input or output or general
purpose I/O pin.
Frame synchronization reference
Receive serial data signal; provided
Transmit Frame synchronization
Chapter 17
Description
17-1