PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 147

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

Table 24
Application
Disable connection
Switched 8 bit channel
Switched 4 bit channel
Switched 4 bit channel
Switched 2 bit channel
Switched 2 bit channel
Switched 2 bit channel
Switched 2 bit channel
Preprocessed channel
Preprocessed channel
Preprocessed channel
W:MAAR
W:MACR
In a next step, the bandwidth of the previously made connection shall be verified:
W:MAAR
W:MACR
wait for STAR:MAC = 0
R:MADR
Table 24 shows all available Control Memory codes.
Examples
In CFI mode 2, CFI time slot 123 shall be initialized as a switched channel. The CM data
field value therefore represents a pointer to the PCM interface.
In a first step, a time slot assignment to PCM port 1, time slot 34 (PCM mode 1) shall be
made for a 64 kbit/s upstream connection:
W:MADR
Semiconductor Group
P channel
= 1100 0110
= 1111 1011
= 0111 0001
= 1111 1011
= 1111 0000
= XXXX 0001
CMC3 … 0
0000
0001
0011
0010
0111
0110
0101
0100
1000
1010
1011
1001
B
B
B
B
B
B
; upstream PCM time slot 34, port 1
; address of upstream CFI time slot 123
; write data + code field command, code “0001”
; address of upstream CFI time slot 123
; read back code field command
; the code “0001” (64 kbit/s channel) is read back
Transferred Bits
–
bits 7 … 0
bits 7 … 4
bits 3 … 0
bits 7 … 6
bits 5 … 4
bits 3 … 2
bits 1 … 0
refer to chapter 5.5
refer to chapter 5.6
and chapter 5.7
147
Channel Bandwidth
unassigned
64 kbit/s
32 kbit/s
32 kbit/s
16 kbit/s
16 kbit/s
16 kbit/s
16 kbit/s
Application Hints
PEB 2055
PEF 2055