PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 83

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

IOM
The IOM-2 standard defines an industry standard serial bus for interconnecting
telecommunications ICs. The standard covers line card, NT1, and terminal architectures
for ISDN, DECT and analog loop applications. The IOM-2 standard is a derivative of the
IOM-1 interface formerly designed by Siemens to interconnect layer-1 and layer-2
devices within ISDN terminals and on digital line cards.
The IOM
individual IOM-1 channels into the 8 kHz frame. The data transfer rate is now increased
to 2.048 Mbit/s, the data is clocked with a double rate clock of 4.096 MHz (DCL) and the
frame is synchronized with an 8 kHz framing signal (FSC). The bit timing and FSC
position differs slightly from the 256 kbit/s IOM-1 interface. The IOM channel structure
however is identical to the non-multiplexed IOM-1 case.
The IOM
5
5.1
5.1.1
user data, control/programming, and status channels for 1 ISDN subscriber, i.e. it
provides capacity for 2 B channels at 64 kbit/s and 1 D channel at 16 kbit/s. The IOM-1
channel consists of four 8 bit time slots which are serially transferred within an 8 kHz
frame. The first 2 time slots carry the B1 and B2 channels, the third time slot carries an
8 bit monitor channel and the fourth time slot carries the 2 bit D channel, a 4 bit
Command/Indication (C/I) channel plus 2 additional control bits (T and E bits). The
monitor channel serves to exchange control and status information in a message
oriented fashion of one byte per message. The C/I channel carries real-time status
information between the line transceiver and the layer-2 device or the line card
controller. Status information transmitted over the C/I channel is “static” in the sense that
the 4 bit word is repeatedly transmitted, every frame, as long as the status condition that
it indicates is valid. The T bit is used by some U layer-1 devices as a transparent
channel. The E bit is used in conjunction with the monitor channel to indicate the transfer
of a monitor byte to the slave device. The various channels are time-multiplexed over a
four wire serial interface. The data transfer rate at the IOM-1 interface is 256 kbit/s, the
data is clocked with a double rate clock of 512 kHz (DCL) and the frame is synchronized
by an 8 kHz framing signal (FSC).
Because the IOM-1 interface structure can handle only 1 ISDN channel, which is too little
for line card applications, the multiplexed IOM
standards. Both the line card and terminal portions of the IOM-2 standard utilize the
same basic frame and clocking structure, but differ in the number and usage of the
individual channels. Data is clocked by a data clock (DCL) that operates at twice the data
Semiconductor Group
®
(ISDN Oriented Modular) Interface
Application Hints
Introduction
IOM
®
®
-1 interface provides a symmetrical full-duplex communication link, containing
-2 bus standard is an enhancement of both the IOM-1 and multiplexed IOM-1
®
and SLD Functions
83
®
-1 bus was developed. It multiplexes 8
Application Hints
PEB 2055
PEF 2055