PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 177

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

Table 27
CM Address
Even time slot downstream
Odd time slot downstream
Even time slot upstream
Odd time slot upstream
Application hint:
Example
In CFI mode 0, time slots 2 and 3 of port 3 are to be initialized for decentral D-Channel
handling:
W:MADR
W:MAAR
W:MACR
W:MADR
W:MAAR
W:MACR
W:MADR
W:MAAR
W:MACR
W:MADR
W:MAAR
W:MACR
detected if the value of the current CFI frame is different from the value of the previous
frame i.e. after at most 125 s.
To initialize two consecutive CFI time slots for the decentral D Channel handling
scheme, the CM codes as given in table 27 must be used.
Semiconductor Group
= 1100 0011
= 0000 1110
= 0111 1000
= XXXX XXXX
= 0000 1111
= 0111 1011
= 1111 1111
= 1000 1110
= 0111 1000
= XXXX XXXX
= 1000 1111
= 0111 0000
If the D-Channel is idle and if it is required to transmit a 2 bit idle
code in the D-Channel (e.g. during the layer-1 activation or for
testing purposes), the 6 bit signaling handling scheme can be
selected for the downstream direction. The 2 D bits together with
the 4 C/I bits can then be written to via the even control memory
address. If the high impedance state is needed again, the
decentral D-Channel scheme has to be selected again.
B
B
B
B
B
B
B
B
B
B
B
B
CM Code
1000
1011
1000
0000
; C/I value ‘0000’
; downstream even TS, port 3 time slot 2
; write CM code + data fields, CM code ‘1000’
; don’t care
; downstream odd TS, port 3 time slot 3
; write CM code + data fields, CM code ‘1011’
; expected C/I value ‘1111’
; upstream even TS, port 3 time slot 2
; write CM code + data fields, CM code ‘1000’
; don’t care
; upstream odd TS, port 3 time slot 3
; write CM code + data fields, CM code ‘0000’
177
CM Data
11 C/I 11
XXXXXXXX
XX C/I XX
XXXXXXXX
B
Application Hints
B
B
B
PEB 2055
PEF 2055