PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 53

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

Access in multiplexed P-interface mode:
CSS
CSM
4.2.2
4.2.2.1 Configurable Interface Mode Register 1 (CMD1)
Access in demultiplexed P-interface mode:
Reset value: 00
CSP1..0
Semiconductor Group
bit 7
CSS
Configurable Interface Registers
Clock Source Selection.
0…PDC and PFS are used as clock and framing source for the CFI. Clock
1…DCL and FSC are selected as clock and framing source for the CFI.
CFI-Synchronization Mode.
The rising FSC edge synchronizes the CFI-frame.
0…FSC is evaluated with every falling edge of DCL.
1…FSC is evaluated with every rising edge of DCL.
Clock Source Prescaler 1,0.
The clock source frequency is divided according to the following table to
obtain the CFI reference clock CRCL.
CSP1,0
00
01
10
11
Note: If CSS = 0 is selected, CSM and PMOD:PSM must be programmed
CSM
and framing signals derived from these sources are output on DCL and
FSC.
H
identical.
CSP1
CSP0
53
CMD1
Prescaler Divisor
2
1.5
1
not allowed
read/write
read/write
Detailed Register Description
CMD0
address: 6
OMDR:RBS = 1
address: 2C
CIS1
PEB 2055
PEF 2055
H
bit 0
H
CIS0