PEB20571F-V31 Infineon Technologies, PEB20571F-V31 Datasheet - Page 13

• Manufacturer Part Number: PEB20571F-V31
• Manufacturer: Infineon Technologies

Specifications of PEB20571F-V31

• Lead Free Status / Rohs Status: Not Compliant

List of Figures
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Data Sheet
Bus Type 138
Bus Type 140
A/µ-law Unit Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
HDLCU General Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
HDLC Data Flow in Receive Direction . . . . . . . . . . . . . . . . . . . . . . . . 117
Data Processing in the GHDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
GHDLC Interface Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Point-to-Multi Point Bus Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
GHDLC Receive and Transmit Buffer Structure . . . . . . . . . . . . . . . . 124
Interframe Time Fill with shared Zero . . . . . . . . . . . . . . . . . . . . . . . . 125
Statistics Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Two-cycle DMA Transfer Mode for Receive Direction . . . . . . . . . . . . 134
Single cycle DMA transfer mode for Receive Data . . . . . . . . . . . . . . 135
Single cycle DMA transfer mode for Transmit Data . . . . . . . . . . . . . . 136
Timing in two-cycle DMA Mode for Transmit Direction and Infineon/ Intel
Timing in two-cycle DMA Mode for Receive Direction and Infineon/ Intel
DELIC Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
TRANSIU Buffer Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
DMA Write-Transaction Timing in Motorola Mode . . . . . . . . . . . . . . . 251
DMA Read-Transaction Timing in Motorola Mode . . . . . . . . . . . . . . . 252
DMA Write-Transaction Timing in Intel/Infineon Mode. . . . . . . . . . . . 254
DMA Read-Transaction Timing in Intel/Infineon Mode . . . . . . . . . . . 254
Write Cycle Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Read Cycle Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Write Cycle Intel/Infineon Demultiplexed Mode . . . . . . . . . . . . . . . . . 258
Read Cycle Intel/Infineon Demultiplexed Mode . . . . . . . . . . . . . . . . . 258
Write Cycle Intel/Infineon Multiplexed Mode . . . . . . . . . . . . . . . . . . . 259
Read Cycle in Intel/Infineon Multiplexed Mode . . . . . . . . . . . . . . . . . 260
Interrupt Acknowledge Cycle Timing in Motorola Mode. . . . . . . . . . . 261
Interrupt Acknowledge Cycle Timing in Intel/Infineon Mode . . . . . . . 261
IREQ Deactivation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
DRDY Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
DCL Timing IOM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
FSC Timing IOM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
PFS Timing in Slave Mode (Input PCM Clocks) . . . . . . . . . . . . . . . . 267
PFS Timing in Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
PFS Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
PDC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
PDC Timing in Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
IOM-2000 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
FSC Timing IOM-2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
PEB 20570
PEB 20571
2003-07-31
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