PEB20571F-V31 Infineon Technologies, PEB20571F-V31 Datasheet - Page 272
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PEB20571F-V31
Manufacturer Part Number
PEB20571F-V31
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEB20571F-V31.pdf
(308 pages)
Specifications of PEB20571F-V31
Lead Free Status / Rohs Status
Not Compliant
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8.6.2
1. By driving the MODE pin ‘high’ the user chooses Motorola Work Mode, by driving it
2. Moreover, there is a difference between work with Multiplexed Address/Data Bus and
8.6.2.1
In this mode R/W distinguishes between Read and Write interactions, and DS is used for
timing.
Table 67
Parameter
R/W setup time before DS x CS rising
edge
R/W hold time after DS x CS rising
edge
A-bus setup time before DS x CS
rising edge
A-bus hold time after DS x CS rising
edge
D-bus setup time before DS x CS
rising edge
D-bus hold time after DS x CS rising
edge
DS X CS pulse width
Note: DS X CS is active (low) when both, DS and CS, are active (low)
Data Sheet
P accesses DELIC by an activation of Address and CS.
‘low’ - Intel/Infineon Work Mode. The pin is sampled by RESET rising edge.
Demultiplexed Address and Data Buses (in Intel/Infineon Mode). In Motorola Mode
Demultiplexed Buses only used. The selection between Multiplexed and
Demultiplexed is done by the manner of use of ALE.
P Access Timing
P Access Timing in Motorola mode
Timing for Write Cycle in Motorola Mode
Electrical Characteristics and Timing Diagrams
Symbol
t
t
t
t
t
t
t
SRWS
HRWS
SAS
HAS
SDS
HDS
WS
255
min.
17
5
22
6
5
8
17
Limit Values
max.
Unit
ns
ns
ns
ns
ns
ns
ns
Notes
Output load
capacity of
50 pF
PEB 20570
PEB 20571
2003-07-31
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