PEB20571F-V31 Infineon Technologies, PEB20571F-V31 Datasheet - Page 208

• Manufacturer Part Number: PEB20571F-V31
• Manufacturer: Infineon Technologies

Specifications of PEB20571F-V31

• Lead Free Status / Rohs Status: Not Compliant

6.2.5
6.2.5.1
In order to enable DSP access all the buffers and RAMS, DSPCTRL bit must be set to ‘1’.
HCR Register
Reset value: 0001
BITOR
HPRS(5:0)
DSPCTRL
Note: Each time DSPCTRL is set, HPRS is also set.
Data Sheet
15
7
x
x
HDLCU Registers Description
HDLCU Control Register
Determines the order of bits inside one HDLC data byte
0 =
1 =
HDLCU Channel Preset
The number of HDLC channels to be processed by the HDLCU
DSP Access Control to the HDLCU
0 =
1 =
BITOR
H
14
6
HDLC data is transmitted/ received with MSB first (default)
HDLC data is transmitted/ received with LSB first
The DSP must not access the HDLCU buffers and RAMs
The DSP may access the HDLCU buffers
13
5
x
12
4
HPRS(5:0)
x
write
191
11
3
x
10
2
x
Register Description
9
x
1
Address: D180
PEB 20570
PEB 20571
DSPCTRL
2003-07-31
8
0
x
H