PEB20571F-V31 Infineon Technologies, PEB20571F-V31 Datasheet - Page 281

• Manufacturer Part Number: PEB20571F-V31
• Manufacturer: Infineon Technologies

Specifications of PEB20571F-V31

• Lead Free Status / Rohs Status: Not Compliant

Table 75
Parameter
DCL Clock Period
DCL Duty Cycle
Note: Usually DSP-clock is generated internally by the internal PLL, in a frequency of
Figure 74
Table 76
Parameter
FSC delay after DCL rising
edge
FSC Clock Period
FSC Clock Period High in a
long-pulse FSC cycle
Data Sheet
DCL
1)
61.44 MHz. If on the other hand a lower frequency clcok is provided via CLK_DSP
input pin, the frequency of DCL should not exceed the frequency of DSP-clock-
frequency / 4 (DSP clcok frequency devided by 4), in order to guarantee a proper
operation of the DELIC.
DCL (IOM-2 Data Clock) Timing
DCL Timing IOM-2
FSC (IOM-2 and IOM-2000 Frame-Sync) Timing
2)
Symbol
t
DCP
Symbo
l
t
t
t
FDE
FSC
HLC
min.
48
Electrical Characteristics and Timing Diagrams
t
Limit Values
DCP
min.
-10
112
typ.
2.604
1.302
651
488
244
50
Limit Values
264
typ.
125
112.5 113
max.
52
max.
10
Unit Notes
ns
ns
ns
%
s
s
Unit Notes
ns
s
s
DCL = 384 kHz
DCL = 768 kHz
DCL = 1536 kHz
DCL = 2048 kHz
DCL = 4096 kHz
Output load capacity
of up to 50 pF on
both, PFS and DCL
8 kHz
PEB 20570
PEB 20571
2003-07-31