PEB20571F-V31 Infineon Technologies, PEB20571F-V31 Datasheet - Page 185

• Manufacturer Part Number: PEB20571F-V31
• Manufacturer: Infineon Technologies

Specifications of PEB20571F-V31

• Lead Free Status / Rohs Status: Not Compliant

6.2.1.5
The Initialization Channel Command Register contains the Command bits for VIP_n,
Channel_m together with 5 bits of the VIP channel address.
The VIP only acts upon the command bits if they were declared valid by the DELIC
issuing a write command. Bit WR is dedicated to the command bits of groups CONF1,
CONF2 and TST2, whereas WR_ST informs the VIP about changes in the layer 1 state
machine of the DELIC (SMINI(2:0) and MSYNC bits).
The DELIC may also explicitly read the VIP’s status information by issuing bit RD.
The reset value of each bit is ’0’ except bits MODE(2:0) which are set to ’011’
Note: A read command to the VIP must not be issued during normal operation to avoid
TICCMR
Reset value: 0000
WR
RD
Data Sheet
a loss of information when the VIP is reporting status information at the same time.
PLLINT
MF_EN
PLLS
31
23
15
x
7
Register
TRANSIU Initialization Channel Command Register
Write Command (S/T, U
0 =
1 =
Read Request to VIP Command Bits (S/T, U
0 =
PD
H
VIPADR(1:0)
30
22
14
6
AAC(1:0)
Data sent in these bits is invalid
All configuration bits contain valid data
Note: Does not apply to SMINI(2:0) and MSYNC bits
Normal operation
MODE(2:0)
DHEN
29
21
13
5
28
20
12
PN
4
x
write
LS-word: D0B0
BBC(1:0)
168
)
CHADR(2:0)
FIL1
27
19
11
MOSEL(1:0)
3
H
PDOWN
,
26
18
10
PN
2
)
Register Description
OWIN(2:0)
LOOP
Address:
MS-word: D0B1
FIL
RD
25
17
9
1
PEB 20570
PEB 20571
2003-07-31
TX_EN
EXLP
WR
24
16
8
0
H