PEB20571F-V31 Infineon Technologies, PEB20571F-V31 Datasheet - Page 283

• Manufacturer Part Number: PEB20571F-V31
• Manufacturer: Infineon Technologies

Specifications of PEB20571F-V31

• Lead Free Status / Rohs Status: Not Compliant

8.6.5
Table 77
Parameter
RxD0..3 setup time before
PDC falling edge
RxD0..3 hold time after
PDC falling edge
PFS setup time before PDC
falling edge
PFS setup time before PDC
rising edge
PFS hold time after PDC
falling edge
PFS hold time after PDC
rising edge
PFS Pulse Width (high)
PFS delay after PDC
PFS Clock Period
PFS Duty Cycle
TxD0..3 delay after PDC
rising edge
TxD0..3 float after PDC
rising edge
TSC0..3 delay after PDC
rising edge
1)
2)
3)
Data Sheet
In 8 kHz PFS - slave mode, PFS is sampled by PDC falling edge. The first PDC cycle in which FSC is sampled
as logic-1 after a sampling of logic-0, is considered as the first cycle of the new PCM frame. Also see
Master/Slave Mode Clocks Selection” on Page 144
In 4 kHz PFS - slave mode, PFS is sampled by PDC rising edge. In order to work appropriately in this mode,
PFS should be sampled as logic-1 only once every frame. The cycle in which PFS is sampled as logic-1 is
considered as the first cycle of the new frame. Also see
Page 144
Inside the DELIC, PFS is also sampled by DSP-clock (61.44 MHz). Since this clock (DSP-clock) is not visible
for the user, a pulse width of more then one 61.44 MHz cycle is required, in order to guarantee an appropriate
sampling.
2)
2)
PCM Interface Timing
1)
1)
PCM Interface Timing
4)
3)
Symb
ol
t
t
t
t
t
t
t
t
t
t
t
t
RPF
RHF
PSP
PPR
HPF
HPR
PPW
PDP
PCP
TPF
TFR
TDR
Electrical Characteristics and Timing Diagrams
min.
10
10
10
10
10
10
25
-10
48
2
2
2
Limit Values
266
typ.
125
50
“PCM Master/Slave Mode Clocks Selection” on
max.
10
52
19
20
19
Unit Notes
ns
ns
ns
ns
ns
ns
ns
ns
%
ns
ns
ns
s
In slave mode, when
PFS and PDC are
inputs.
In master mode,
when PFS and PDC
are outputs.
TxD0..3
PEB 20570
PEB 20571
2003-07-31
“PCM