MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet
MT48LC16M16LFFG
Specifications of MT48LC16M16LFFG
Related parts for MT48LC16M16LFFG
MT48LC16M16LFFG Summary of contents
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... See our Web site for more information on abbreviated component marks. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE ...
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... Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 PIN ASSIGNMENT (Top View) 54-Pin TSOP x16 DQ0 DQ1 4 DQ2 5 VssQ 6 DQ3 7 DQ4 DQ5 10 DQ6 11 VssQ 12 DQ7 DQML 15 WE# 16 CAS# 17 RAS# 18 CS# 19 BA0 20 BA1 21 A10 PRELIMINARY 256Mb: x16 MOBILE SDRAM x16 54 Vss 53 DQ15 ...
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... SDRAM PART NUMBERS 1 PART NUMBER MT48LC16M16LFFG-10 MT48LC16M16LFFG-8 MT48V16M16LFFG-10 MT48V16M16LFFG-8 MT48H16M16LFFG-10 MT48H16M16LFFG-8 MT48LC16M16LFTG-10 MT48LC16M16LFTG-8 MT48V16M16LFTG-10 MT48V16M16LFTG-8 MT48H16M16LFTG-10 MT48H16M16LFTG-8 Note: 1. Lead-Free packaging partnumbers: Replace the FG with BG for VFBGA and replace the TG code with P for TSOP. GENERAL DESCRIPTION The 256Mb SDRAM is a high-speed CMOS, ...
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... Operation .................................................................... 16 Bank/Row Activation ........................................... 16 Reads ....................................................................... 17 Writes ....................................................................... 23 Precharge ................................................................. 25 Power-Down .......................................................... 25 Deep Power-Down ................................................ 26 Clock Suspend ........................................................ 26 Burst Read/Single Write ........................................ 27 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 5 Concurrent Auto Precharge ................................. 28 6 Truth Table 2 (CKE) 7 Truth Table 3 (Current State, Same Bank) Truth Table 4 (Current State, Different Bank) 8 Absolute Maximum Ratings ...
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... CAS# RAS# REFRESH COUNTER MODE REGISTER 12 13 A0-A12, ADDRESS 15 BA0, BA1 REGISTER 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 FUNCTIONAL BLOCK DIAGRAM 16 Meg x 16 SDRAM 13 BANK0 ROW- 13 ROW- ADDRESS ADDRESS MUX 8192 LATCH & (8,192 x 512 x 16) DECODER SENSE AMPLIFIERS ...
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... Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 TYPE Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. ...
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... Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 TYPE Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal ...
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... FUNCTIONAL DESCRIPTION In general, the 256Mb SDRAMs (4 Meg banks) are quad-bank DRAMs that operate at 3.3V or 2.5V or 1.8V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. ...
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... M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices M6- Defined - - Write Burst Mode M9 0 Programmed Burst Length 1 Single Location Access 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 Burst Length Address Bus Mode Register (Mx) Burst Length Burst Length ...
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... D OUT DQ n CAS Latency = 3 NOTE: Each READ command may be to either bank. DQM is LOW. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero ...
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... This allows great power savings during SELF REFRESH during most operating tempera- ture ranges. Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher tempera- tures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often ...
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... SELF REFRESH. There are four temperature settings, which will vary the SELF REFRESH current according to the selected temperature. This selectable refresh rate will save power when the DRAM is operating at normal temperatures. PARTIAL ARRAY SELF REFRESH For further power savings during SELF REFRESH, ...
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... Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). 9. Standard SDRAM parts assign this command sequence as Burst Terminate. For Mobile SDRAM parts, the Burst Terminate command is assigned to the Deep Power Down function. ...
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... SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ...
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... RC), once every 64ms. SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 ...
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... Operation BANK/ROW ACTIVATION Before any READ or WRITE commands can be is- sued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the AC- TIVE command, which selects both the bank and the row to be activated (see Figure 3). ...
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... A9, A11: x16 ENABLE AUTO PRECHARGE A10 DISABLE AUTO PRECHARGE BA0,1 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 Upon completion of a burst, assuming no other com- mands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to the start address and continue ...
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... This is shown in Figure 7 for CAS latencies of two and three; data element either the last of a burst of four or the last desired of a longer burst. The 256Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch CLK COMMAND ...
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... CLK COMMAND ADDRESS DQ CAS Latency = 1 CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ NOTE: Each READ command may be to either bank. DQM is LOW. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 Figure 8 Random READ Accesses READ READ READ READ BANK, BANK, BANK, BANK, ...
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... I/O contention can be avoided given system design, there may be a possibility that the device driv- ing the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command ...
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... BANK a, ADDRESS COL n DQ NOTE: DQM is LOW. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until that part of the row precharge time is hidden during the access of the last data element(s) ...
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... CLK COMMAND ADDRESS DQ NOTE: DQM is LOW. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 command, provided that auto precharge was not acti- vated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 12 for each possible CAS latency ...
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... MOBILE SDRAM ample is shown in Figure 15. Data either the last of a burst of two or the last desired of a longer burst. The 256Mb SDRAM uses a pipelined architecture and there- fore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initi- ated on any clock cycle following a previous WRITE command ...
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... TRANSITIONING DATA NOTE: The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW. CAS latency = 2 for illustration. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 requires a of frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coinci- dent with, the PRECHARGE command ...
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... All Banks A10 Bank Selected BANK BA0, BA1 ADDRESS 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 PRECHARGE The PRECHARGE command (see Figure 20) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time ( ter the PRECHARGE command is issued ...
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... Enter deep power-down mode. Exit deep power-down mode. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 CLOCK SUSPEND The clock suspend mode occurs when a column ac- cess/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deacti- vated, “ ...
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... READ commands access columns according to the pro- grammed burst length and sequence, just as in the normal mode of operation (M9 = 0). 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 MOBILE SDRAM Figure 23 Clock Suspend During READ Burst ...
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... CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. Micron SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. ...
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... COMMAND BANK n Internal States BANK m ADDRESS DQ NOTE: 1. DQM is LOW. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 4. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after t where WR begins when registered ...
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... After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge Deep Power-Down is a power savings feature of this Mobile SDRAM device. This command is Burst Terminate on traditional SDRAM components. For Mobile SDRAM devices, this command sequence is assigned to Deep Power Down. ...
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... Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when has been met. Once Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when has been met. Once 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 COMMAND (ACTION) X COMMAND INHIBIT (NOP/Continue previous operation) ...
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... May or may not be bank-specific; if all banks are to be precharged, all must valid state for precharging. 9. Deep Power-Down is a power savings feature of this Mobile SDRAM device. This command is Burst Terminate on traditional SDRAM components. For Mobile SDRAM devices, this command sequence is assigned to Deep Power Down. ...
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... Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when has been met. Once Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when has been met. Once 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 COMMAND (ACTION) X COMMAND INHIBIT (NOP/Continue previous operation) ...
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... WRITE on bank n when registered. The PRECHARGE to bank n will begin after begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 27). 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/ begins when the READ to bank m is registered ...
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... IN DD OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V ≤ V 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional ...
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... Input Capacitance: All other input-only pins Input/Output Capacitance: DQs CAPACITANCE – TSOP (Note: 2; notes appear on page 40) PARAMETER Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 = 1.8 ±0.15V +1.8V ±0.15V ) DD DDQ SYMBOL V ...
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... ACTIVE to READ or WRITE delay Refresh period (8,192 rows) AUTO REFRESH period PRECHARGE cmd period ACTIVE bank a to bank b command Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 -8 SYMBOL MIN MAX MIN t ...
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... Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 MOBILE SDRAM SYMBOL t CCD ...
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... I - SELF REFRESH CURRENT OPTIONS (Temperature Compensated Self Refresh (Notes 11, 13; notes appear on page 40 1.8V ±0.15V Temperature Compensated Self Refresh Parameter/Condition Self Refresh Current: CKE < 0.2V 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/ 3.3 ±0.3V (MIN RFC = RFC (MIN) t RFC = 7.8µ 3.3 ± ...
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... Timing actually specified by fied as a reference only at minimum cycle rate. 15. Timing actually specified by specified as a reference only at minimum cycle rate. 16. Timing actually specified by 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 . 17. Required clocks are specified by JEDEC function- = 25° +2.5V ...
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... The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order. However, all must occur prior to an Active command. 5. Device timing is -10 with 100MHz clock. TIMING PARAMETERS -8 SYMBOL* MIN MAX (1) 20 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/ ...
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... NOTE: 1. Violating refresh requirements during power-down may result in a loss of data. TIMING PARAMETERS -8 SYMBOL* MIN MAX 2 ( (2) 10 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 POWER-DOWN MODE CKS NOP NOP Input buffers gated off while in power-down mode Exit power-down mode -10 MIN MAX UNITS SYMBOL (1) t 2.5 ns ...
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... A9, A11 and A12 = “Don’t Care” TIMING PARAMETERS -8 SYMBOL* MIN MAX (1) 20 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 CLOCK SUSPEND MODE CKS t CKH NOP NOP OUT t LZ -10 SYMBOL* MIN MAX UNITS CKH t CKS CMH ...
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... Precharge all active banks NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required. TIMING PARAMETERS -8 SYMBOL* MIN MAX 2 ( (2) 10 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 AUTO REFRESH MODE AUTO NOP NOP NOP ( ...
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... XSR requires minimum of two clocks regardless of frequency and timing general rule, any time Self Refresh is exited, the DRAM may not re-enter the Self Refresh Mode until all rows have been refreshed via the Auto Refresh command at the distributed refresh rate, following exception is allowed. Self Refresh mode may be re-entered any time after exiting, provided all of the following conditions are met: a ...
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... CKH 1 t CKS 2.5 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 READ – WITHOUT AUTO PRECHARGE READ NOP NOP t CMS t CMH COLUMN m 2 BANK OUT t LZ CAS Latency -10 MIN MAX UNITS SYMBOL CMH CMS t 22 ...
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... CKH 1 t CKS 2.5 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 READ – WITH AUTO PRECHARGE READ NOP NOP t CMS t CMH COLUMN m 2 BANK OUT t LZ CAS Latency -10 MIN MAX UNITS SYMBOL CMH CMS t 22 ...
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... SYMBOL* MIN MAX CKH 1 t CKS 2.5 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/ PRECHARGE READ NOP NOP t CMS t CMH 3 COLUMN m SINGLE BANKS BANK OUT CAS Latency t RAS would be violated. -10 MIN MAX UNITS SYMBOL CMH CMS ...
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... CKH 1 t CKS 2.5 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/ NOP 2 NOP 2 READ t CMS t CMH COLUMN m 3 ENABLE AUTO PRECHARGE BANK CAS Latency t RAS would be violated since AUTO PRECHARGE is enabled. -10 MIN MAX UNITS SYMBOL CMH ...
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... MIN MAX CKH 1 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/ READ NOP ACTIVE t CMS t CMH COLUMN m 2 ROW ROW BANK 0 BANK OUT t LZ CAS Latency - BANK 0 t RCD - BANK 1 -10 MIN MAX UNITS SYMBOL CKS 8 ns ...
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... (1) 20 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 READ – FULL-PAGE BURST READ NOP NOP NOP t CMH BANK m+1 OUT OUT t LZ 512 (x16) locations within same row 1,024 (x8) locations within same row 2,048 (x4) locations within same row CAS Latency Full-page burst does not self-terminate ...
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... A9, A11 and A12 = “Don’t Care” TIMING PARAMETERS -8 SYMBOL* MIN MAX (1) 20 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 READ – DQM OPERATION READ NOP NOP t CMS t CMH COLUMN m 2 BANK OUT CAS Latency -10 MIN MAX UNITS SYMBOL CKH CKS ...
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... TIMING PARAMETERS -8 SYMBOL* MAX MIN CKH 1 t CKS 2.5 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 WRITE – WITHOUT AUTO PRECHARGE WRITE NOP NOP t CMH COLUMN m 2 BANK m> and the PRECHARGE command, regardless of frequency. IN -10 ...
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... A9, A11 and A12 = “Don’t Care” TIMING PARAMETERS -8 SYMBOL* MIN MAX CKH 1 t CKS 2.5 t CMH 1 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 WRITE – WITH AUTO PRECHARGE WRITE NOP NOP t CMH 2 m COLUMN BANK -10 MIN MAX UNITS SYMBOL* t ...
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... MAX CKH 1 t CKS 2.5 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/ NOP 2 NOP 2 WRITE t CMS t CMH COLUMN m 3 BANK RAS would be violated. m> and the PRECHARGE command, regardless of frequency. With a single write IN t RAS requirement. -10 SYMBOL* ...
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... TIMING PARAMETERS -8 SYMBOL* MIN MAX CKH 1 t CKS 2.5 t CMH 1 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/ NOP 2 NOP 2 WRITE NOP t CMS t CMH COLUMN m 3 ENABLE AUTO PRECHARGE BANK RAS would be violated. -10 MIN MAX UNITS SYMBOL CMS t 2.5 ...
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... A9, A11 and A12 = “Don’t Care” TIMING PARAMETERS -8 SYMBOL* MIN MAX CKH 1 t CKS 2.5 t CMH 1 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/ WRITE NOP ACTIVE t CMH COLUMN m 3 ROW ROW BANK 0 BANK RCD - BANK 1 -10 MIN MAX UNITS ...
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... WR must be satisfied prior to PRECHARGE command. 3. Page left open RP. TIMING PARAMETERS -8 SYMBOL* MIN MAX (1) 20 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 WRITE – FULL-PAGE BURST WRITE NOP NOP t CMH t CMS 1 m COLUMN BANK 512 (x16) locations within same row ...
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... A9, A11 and A12 = “Don’t Care” TIMING PARAMETERS -8 SYMBOL* MIN MAX (1) 20 *CAS latency indicated in parentheses. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 WRITE – DQM OPERATION WRITE NOP NOP t CMS t CMH COLUMN m 2 ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK -10 MIN MAX ...
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... PIN #1 ID .75 (2X) 1.00 (2X) NOTE: 1. All dimensions in millimeters or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 54-PIN PLASTIC TSOP (400 mil) .71 .10 (2X) 2.80 11 ...
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... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. 256Mb: x16 Mobile SDRAM MobileRamY26L_B.p65 – Pub. 04/03 VFBGA “FG” PACKAGE 54-pin, 8mm x 14mm 0.155 ± ...