MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 7

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
PIN DESCRIPTIONS
2, 4, 5, 7, 8, 10, 11, 13, 42, DQ0-DQ15
23-26, 29-34, 22, 35, 36
44, 45, 47, 48, 50, 51, 53
54-PIN TSOP
6, 12, 46, 52
3, 9, 43, 49
16, 17, 18
28, 41, 54
1, 14, 27
15, 39
20, 21
38
37
19
40
WE#, CAS#,
x16: DQML,
SYMBOL
BA0, BA1
A0-A12
DQMU
V
RAS#
V
CKE
CLK
CS#
V
NC
V
DD
SS
DD
SS
Q
Q
x16: I/O Data Input/Output: Data bus for x16
Supply DQ Power: Isolated DQ power to the die for improved noise immunity.
Supply DQ Ground: Isolated DQ ground to the die for improved noise
Supply Power Supply: Voltage dependant on option.
Supply Ground.
TYPE
Input
Input
Input
Input
Input
Input
Input
–
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN
(row active in any bank) or CLOCK SUSPEND operation (burst/access in
progress). CKE is synchronous except after the device enters power-
down and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
Chip Select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.
Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the
command being entered.
Input/Output Mask: DQM is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked when
DQM is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQM is sampled
HIGH during a READ cycle. On the x16, DQML corresponds to DQ0-
DQ7 and DQMH corresponds to DQ8-DQ15. DQML and DQMH are
considered same state when referenced as DQM.
Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
Address Inputs: A0-A12 are sampled during the ACTIVE command
(row-address A0-A12) and READ/WRITE command (column-address
A0-A8 [x16]; with A10 defining auto precharge) to select one location
out of the memory array in the respective bank. A10 is sampled during
a PRECHARGE command to determine if all banks are to be precharged
(A10 [HIGH]) or bank selected by (A10 [LOW]). The address inputs also
provide the op-code during a LOAD MODE REGISTER command.
No Connect: This pin should be left unconnected.
immunity.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x16
PRELIMINARY