MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 22

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropri-
ate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to trun-
cate fixed-length or full-page bursts.
BURST TERMINATE command, and fixed-length READ
bursts may be truncated with a BURST TERMINATE
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
Full-page READ bursts can be truncated with the
COMMAND
COMMAND
COMMAND
ADDRESS
ADDRESS
ADDRESS
NOTE: DQM is LOW.
CLK
CLK
CLK
DQ
DQ
DQ
CAS Latency = 1
BANK,
BANK,
T0
COL n
T0
COL n
T0
BANK,
COL n
READ
READ
READ
CAS Latency = 2
CAS Latency = 3
Terminating a READ Burst
T1
T1
T1
NOP
NOP
NOP
D
OUT
n
T2
T2
T2
NOP
NOP
NOP
D
D
n + 1
OUT
OUT
n
Figure 12
T3
T3
T3
NOP
NOP
NOP
22
D
n + 2
D
D
n + 1
OUT
OUT
OUT
n
command, provided that auto precharge was not acti-
vated. The BURST TERMINATE command should be
issued x cycles before the clock edge at which the last
desired data element is valid, where x equals the CAS
latency minus one. This is shown in Figure 12 for each
possible CAS latency; data element n + 3 is the last
desired data element of a longer burst.
TRANSITIONING DATA
TERMINATE
TERMINATE
TERMINATE
T4
BURST
T4
BURST
T4
BURST
X = 0 cycles
X = 1 cycle
D
n + 2
D
n + 3
D
n + 1
OUT
OUT
OUT
X = 2 cycles
T5
T5
T5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
NOP
NOP
D
n + 3
D
n + 2
OUT
OUT
T6
T6
T6
NOP
NOP
NOP
D
n + 3
OUT
DON’T CARE
T7
NOP
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x16
PRELIMINARY