MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 3

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

256Mb SDRAM PART NUMBERS
MT48LC16M16LFTG-10
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
Note: 1. Lead-Free packaging partnumbers: Replace the FG with BG for VFBGA and replace the TG code with P for TSOP.
GENERAL DESCRIPTION
dynamic
268,435,456 bits. It is internally configured as a quad-
bank DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the x16’s 67,108,864-bit banks is orga-
nized as 8,192 rows by 512 columns by 16 bits.
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0, BA1
select the bank; A0–A12 select the row). The address
bits registered coincident with the READ or WRITE com-
mand are used to select the starting column location
for the burst access.
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.
PART NUMBER
MT48LC16M16LFFG-10
MT48LC16M16LFFG-8
MT48V16M16LFFG-10
MT48V16M16LFFG-8
MT48H16M16LFFG-10
MT48H16M16LFFG-8
MT48LC16M16LFTG-8
MT48V16M16LFTG-10
MT48V16M16LFTG-8
MT48H16M16LFTG-10
MT48H16M16LFTG-8
The 256Mb SDRAM is a high-speed CMOS,
Read and write accesses to the SDRAM are burst
The SDRAM provides for programmable READ or
random-access
1
memory
3.3V / 3.3V
3.3V / 3.3V
2.5V / 1.8V
2.5V / 1.8V
1.8V / 1.8V
1.8V / 1.8V
3.3V / 3.3V
3.3V / 3.3V
2.5V / 1.8V
2.5V / 1.8V
1.8V / 1.8V
1.8V / 1.8V
V
DD
/V
DD
containing
Q
3
chitecture to achieve high-speed operation. This ar-
chitecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-
speed, random-access operation.
or 2.5V or 1.8V memory systems. An auto refresh mode
is provided, along with a power-saving, power-down
mode. All inputs and outputs are LVTTL-compatible.
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks to hide precharge time and
the capability to randomly change column addresses
on each clock cycle during a burst access.
ARCHITECTURE
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
The 256Mb SDRAM uses an internal pipelined ar-
The 256Mb SDRAM is designed to operate in 3.3V
SDRAMs offer substantial advances in DRAM oper-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MOBILE SDRAM
54-BALL VFBGA
54-BALL VFBGA
54-BALL VFBGA
54-BALL VFBGA
54-BALL VFBGA
54-BALL VFBGA
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x16
PACKAGE
54-PIN TSOP
54-PIN TSOP
54-PIN TSOP
54-PIN TSOP
54-PIN TSOP
54-PIN TSOP
PRELIMINARY